1 /* 2 * K2G EVM : Board initialization 3 * 4 * (C) Copyright 2015 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 #include <common.h> 10 #include <asm/arch/clock.h> 11 12 #define SYS_CLK 24000000 13 14 unsigned int external_clk[ext_clk_count] = { 15 [sys_clk] = SYS_CLK, 16 [pa_clk] = SYS_CLK, 17 [tetris_clk] = SYS_CLK, 18 [ddr3a_clk] = SYS_CLK, 19 [uart_clk] = SYS_CLK, 20 }; 21 22 static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4}; 23 static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4}; 24 static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4}; 25 static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2}; 26 static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10}; 27 28 struct pll_init_data *get_pll_init_data(int pll) 29 { 30 struct pll_init_data *data = NULL; 31 32 switch (pll) { 33 case MAIN_PLL: 34 data = &main_pll_config; 35 break; 36 case TETRIS_PLL: 37 data = &tetris_pll_config[speed]; 38 break; 39 case NSS_PLL: 40 data = &nss_pll_config; 41 break; 42 case UART_PLL: 43 data = &uart_pll_config; 44 break; 45 case DDR3_PLL: 46 data = &ddr_pll_config; 47 break; 48 default: 49 data = NULL; 50 } 51 52 return data; 53 } 54 55 s16 divn_val[16] = { 56 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 57 }; 58 59 #ifdef CONFIG_BOARD_EARLY_INIT_F 60 int board_early_init_f(void) 61 { 62 init_plls(); 63 64 return 0; 65 } 66 #endif 67 68 #ifdef CONFIG_SPL_BUILD 69 void spl_init_keystone_plls(void) 70 { 71 init_plls(); 72 } 73 #endif 74