1 /* 2 * K2E EVM : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/ddr3.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/ti-common/keystone_net.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 unsigned int external_clk[ext_clk_count] = { 18 [sys_clk] = 100000000, 19 [alt_core_clk] = 100000000, 20 [pa_clk] = 100000000, 21 [ddr3_clk] = 100000000, 22 [mcm_clk] = 312500000, 23 [pcie_clk] = 100000000, 24 [sgmii_clk] = 156250000, 25 [xgmii_clk] = 156250000, 26 [usb_clk] = 100000000, 27 }; 28 29 static struct pll_init_data core_pll_config[NUM_SPDS] = { 30 [SPD800] = CORE_PLL_800, 31 [SPD850] = CORE_PLL_850, 32 [SPD1000] = CORE_PLL_1000, 33 [SPD1250] = CORE_PLL_1250, 34 [SPD1350] = CORE_PLL_1350, 35 [SPD1400] = CORE_PLL_1400, 36 [SPD1500] = CORE_PLL_1500, 37 }; 38 39 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 40 int speeds[DEVSPEED_NUMSPDS] = { 41 SPD850, 42 SPD1000, 43 SPD1250, 44 SPD1350, 45 SPD1400, 46 SPD1500, 47 SPD1400, 48 SPD1350, 49 SPD1250, 50 SPD1000, 51 SPD850, 52 SPD800, 53 }; 54 55 s16 divn_val[16] = { 56 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 57 }; 58 59 static struct pll_init_data pa_pll_config = 60 PASS_PLL_1000; 61 62 struct pll_init_data *get_pll_init_data(int pll) 63 { 64 int speed; 65 struct pll_init_data *data; 66 67 switch (pll) { 68 case MAIN_PLL: 69 speed = get_max_dev_speed(); 70 data = &core_pll_config[speed]; 71 break; 72 case PASS_PLL: 73 data = &pa_pll_config; 74 break; 75 default: 76 data = NULL; 77 } 78 79 return data; 80 } 81 82 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 83 struct eth_priv_t eth_priv_cfg[] = { 84 { 85 .int_name = "K2E_EMAC0", 86 .rx_flow = 0, 87 .phy_addr = 0, 88 .slave_port = 1, 89 .sgmii_link_type = SGMII_LINK_MAC_PHY, 90 }, 91 { 92 .int_name = "K2E_EMAC1", 93 .rx_flow = 8, 94 .phy_addr = 1, 95 .slave_port = 2, 96 .sgmii_link_type = SGMII_LINK_MAC_PHY, 97 }, 98 { 99 .int_name = "K2E_EMAC2", 100 .rx_flow = 16, 101 .phy_addr = 2, 102 .slave_port = 3, 103 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 104 }, 105 { 106 .int_name = "K2E_EMAC3", 107 .rx_flow = 24, 108 .phy_addr = 3, 109 .slave_port = 4, 110 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 111 }, 112 { 113 .int_name = "K2E_EMAC4", 114 .rx_flow = 32, 115 .phy_addr = 4, 116 .slave_port = 5, 117 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 118 }, 119 { 120 .int_name = "K2E_EMAC5", 121 .rx_flow = 40, 122 .phy_addr = 5, 123 .slave_port = 6, 124 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 125 }, 126 { 127 .int_name = "K2E_EMAC6", 128 .rx_flow = 48, 129 .phy_addr = 6, 130 .slave_port = 7, 131 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 132 }, 133 { 134 .int_name = "K2E_EMAC7", 135 .rx_flow = 56, 136 .phy_addr = 7, 137 .slave_port = 8, 138 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 139 }, 140 }; 141 142 int get_num_eth_ports(void) 143 { 144 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 145 } 146 #endif 147 148 #if defined(CONFIG_BOARD_EARLY_INIT_F) 149 int board_early_init_f(void) 150 { 151 init_plls(); 152 153 return 0; 154 } 155 #endif 156 157 #ifdef CONFIG_SPL_BUILD 158 void spl_init_keystone_plls(void) 159 { 160 init_plls(); 161 } 162 #endif 163