1 /* 2 * Keystone : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include "board.h" 11 #include <common.h> 12 #include <spl.h> 13 #include <exports.h> 14 #include <fdt_support.h> 15 #include <asm/arch/ddr3.h> 16 #include <asm/arch/psc_defs.h> 17 #include <asm/ti-common/ti-aemif.h> 18 #include <asm/ti-common/keystone_net.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 static struct aemif_config aemif_configs[] = { 23 { /* CS0 */ 24 .mode = AEMIF_MODE_NAND, 25 .wr_setup = 0xf, 26 .wr_strobe = 0x3f, 27 .wr_hold = 7, 28 .rd_setup = 0xf, 29 .rd_strobe = 0x3f, 30 .rd_hold = 7, 31 .turn_around = 3, 32 .width = AEMIF_WIDTH_8, 33 }, 34 }; 35 36 int dram_init(void) 37 { 38 ddr3_init(); 39 40 gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 41 CONFIG_MAX_RAM_BANK_SIZE); 42 aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); 43 return 0; 44 } 45 46 int board_init(void) 47 { 48 gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; 49 50 return 0; 51 } 52 53 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 54 int get_eth_env_param(char *env_name) 55 { 56 char *env; 57 int res = -1; 58 59 env = getenv(env_name); 60 if (env) 61 res = simple_strtol(env, NULL, 0); 62 63 return res; 64 } 65 66 int board_eth_init(bd_t *bis) 67 { 68 int j; 69 int res; 70 int port_num; 71 char link_type_name[32]; 72 73 /* By default, select PA PLL clock as PA clock source */ 74 if (psc_enable_module(KS2_LPSC_PA)) 75 return -1; 76 if (psc_enable_module(KS2_LPSC_CPGMAC)) 77 return -1; 78 if (psc_enable_module(KS2_LPSC_CRYPTO)) 79 return -1; 80 81 port_num = get_num_eth_ports(); 82 83 for (j = 0; j < port_num; j++) { 84 sprintf(link_type_name, "sgmii%d_link_type", j); 85 res = get_eth_env_param(link_type_name); 86 if (res >= 0) 87 eth_priv_cfg[j].sgmii_link_type = res; 88 89 keystone2_emac_initialize(ð_priv_cfg[j]); 90 } 91 92 return 0; 93 } 94 #endif 95 96 #ifdef CONFIG_SPL_BUILD 97 void spl_board_init(void) 98 { 99 spl_init_keystone_plls(); 100 preloader_console_init(); 101 } 102 103 u32 spl_boot_device(void) 104 { 105 #if defined(CONFIG_SPL_SPI_LOAD) 106 return BOOT_DEVICE_SPI; 107 #else 108 puts("Unknown boot device\n"); 109 hang(); 110 #endif 111 } 112 #endif 113 114 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 115 void ft_board_setup(void *blob, bd_t *bd) 116 { 117 int lpae; 118 char *env; 119 char *endp; 120 int nbanks; 121 u64 size[2]; 122 u64 start[2]; 123 char name[32]; 124 int nodeoffset; 125 u32 ddr3a_size; 126 int unitrd_fixup = 0; 127 128 env = getenv("mem_lpae"); 129 lpae = env && simple_strtol(env, NULL, 0); 130 env = getenv("uinitrd_fixup"); 131 unitrd_fixup = env && simple_strtol(env, NULL, 0); 132 133 ddr3a_size = 0; 134 if (lpae) { 135 env = getenv("ddr3a_size"); 136 if (env) 137 ddr3a_size = simple_strtol(env, NULL, 10); 138 if ((ddr3a_size != 8) && (ddr3a_size != 4)) 139 ddr3a_size = 0; 140 } 141 142 nbanks = 1; 143 start[0] = bd->bi_dram[0].start; 144 size[0] = bd->bi_dram[0].size; 145 146 /* adjust memory start address for LPAE */ 147 if (lpae) { 148 start[0] -= CONFIG_SYS_SDRAM_BASE; 149 start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; 150 } 151 152 if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { 153 size[1] = ((u64)ddr3a_size - 2) << 30; 154 start[1] = 0x880000000; 155 nbanks++; 156 } 157 158 /* reserve memory at start of bank */ 159 sprintf(name, "mem_reserve_head"); 160 env = getenv(name); 161 if (env) { 162 start[0] += ustrtoul(env, &endp, 0); 163 size[0] -= ustrtoul(env, &endp, 0); 164 } 165 166 sprintf(name, "mem_reserve"); 167 env = getenv(name); 168 if (env) 169 size[0] -= ustrtoul(env, &endp, 0); 170 171 fdt_fixup_memory_banks(blob, start, size, nbanks); 172 173 /* Fix up the initrd */ 174 if (lpae && unitrd_fixup) { 175 int err; 176 u32 *prop1, *prop2; 177 u64 initrd_start, initrd_end; 178 179 nodeoffset = fdt_path_offset(blob, "/chosen"); 180 if (nodeoffset >= 0) { 181 prop1 = (u32 *)fdt_getprop(blob, nodeoffset, 182 "linux,initrd-start", NULL); 183 prop2 = (u32 *)fdt_getprop(blob, nodeoffset, 184 "linux,initrd-end", NULL); 185 if (prop1 && prop2) { 186 initrd_start = __be32_to_cpu(*prop1); 187 initrd_start -= CONFIG_SYS_SDRAM_BASE; 188 initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; 189 initrd_start = __cpu_to_be64(initrd_start); 190 initrd_end = __be32_to_cpu(*prop2); 191 initrd_end -= CONFIG_SYS_SDRAM_BASE; 192 initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; 193 initrd_end = __cpu_to_be64(initrd_end); 194 195 err = fdt_delprop(blob, nodeoffset, 196 "linux,initrd-start"); 197 if (err < 0) 198 puts("error deleting initrd-start\n"); 199 200 err = fdt_delprop(blob, nodeoffset, 201 "linux,initrd-end"); 202 if (err < 0) 203 puts("error deleting initrd-end\n"); 204 205 err = fdt_setprop(blob, nodeoffset, 206 "linux,initrd-start", 207 &initrd_start, 208 sizeof(initrd_start)); 209 if (err < 0) 210 puts("error adding initrd-start\n"); 211 212 err = fdt_setprop(blob, nodeoffset, 213 "linux,initrd-end", 214 &initrd_end, 215 sizeof(initrd_end)); 216 if (err < 0) 217 puts("error adding linux,initrd-end\n"); 218 } 219 } 220 } 221 } 222 223 void ft_board_setup_ex(void *blob, bd_t *bd) 224 { 225 int lpae; 226 u64 size; 227 char *env; 228 u64 *reserve_start; 229 230 env = getenv("mem_lpae"); 231 lpae = env && simple_strtol(env, NULL, 0); 232 233 if (lpae) { 234 /* 235 * the initrd and other reserved memory areas are 236 * embedded in in the DTB itslef. fix up these addresses 237 * to 36 bit format 238 */ 239 reserve_start = (u64 *)((char *)blob + 240 fdt_off_mem_rsvmap(blob)); 241 while (1) { 242 *reserve_start = __cpu_to_be64(*reserve_start); 243 size = __cpu_to_be64(*(reserve_start + 1)); 244 if (size) { 245 *reserve_start -= CONFIG_SYS_SDRAM_BASE; 246 *reserve_start += 247 CONFIG_SYS_LPAE_SDRAM_BASE; 248 *reserve_start = 249 __cpu_to_be64(*reserve_start); 250 } else { 251 break; 252 } 253 reserve_start += 2; 254 } 255 } 256 } 257 #endif 258