1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <linux/string.h> 17 #include <asm/gpio.h> 18 #include <usb.h> 19 #include <linux/usb/gadget.h> 20 #include <asm/omap_common.h> 21 #include <asm/omap_sec_common.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/dra7xx_iodelay.h> 24 #include <asm/emif.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/mmc_host_def.h> 27 #include <asm/arch/sata.h> 28 #include <environment.h> 29 #include <dwc3-uboot.h> 30 #include <dwc3-omap-uboot.h> 31 #include <ti-usb-phy-uboot.h> 32 #include <miiphy.h> 33 34 #include "mux_data.h" 35 #include "../common/board_detect.h" 36 37 #define board_is_dra74x_evm() board_ti_is("5777xCPU") 38 #define board_is_dra72x_evm() board_ti_is("DRA72x-T") 39 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ 40 (strncmp("H", board_ti_get_rev(), 1) <= 0)) 41 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ 42 (strncmp("C", board_ti_get_rev(), 1) <= 0)) 43 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ 44 board_ti_get_emif2_size() 45 46 #ifdef CONFIG_DRIVER_TI_CPSW 47 #include <cpsw.h> 48 #endif 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 /* GPIO 7_11 */ 53 #define GPIO_DDR_VTT_EN 203 54 55 #define SYSINFO_BOARD_NAME_MAX_LEN 37 56 57 const struct omap_sysinfo sysinfo = { 58 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" 59 }; 60 61 static const struct emif_regs emif1_ddr3_532_mhz_1cs = { 62 .sdram_config_init = 0x61851ab2, 63 .sdram_config = 0x61851ab2, 64 .sdram_config2 = 0x08000000, 65 .ref_ctrl = 0x000040F1, 66 .ref_ctrl_final = 0x00001035, 67 .sdram_tim1 = 0xCCCF36B3, 68 .sdram_tim2 = 0x308F7FDA, 69 .sdram_tim3 = 0x427F88A8, 70 .read_idle_ctrl = 0x00050000, 71 .zq_config = 0x0007190B, 72 .temp_alert_config = 0x00000000, 73 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 74 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 75 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 76 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 77 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 78 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 79 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 80 .emif_rd_wr_lvl_rmp_win = 0x00000000, 81 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 82 .emif_rd_wr_lvl_ctl = 0x00000000, 83 .emif_rd_wr_exec_thresh = 0x00000305 84 }; 85 86 static const struct emif_regs emif2_ddr3_532_mhz_1cs = { 87 .sdram_config_init = 0x61851B32, 88 .sdram_config = 0x61851B32, 89 .sdram_config2 = 0x08000000, 90 .ref_ctrl = 0x000040F1, 91 .ref_ctrl_final = 0x00001035, 92 .sdram_tim1 = 0xCCCF36B3, 93 .sdram_tim2 = 0x308F7FDA, 94 .sdram_tim3 = 0x427F88A8, 95 .read_idle_ctrl = 0x00050000, 96 .zq_config = 0x0007190B, 97 .temp_alert_config = 0x00000000, 98 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 99 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 100 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 101 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 102 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 103 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 104 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 105 .emif_rd_wr_lvl_rmp_win = 0x00000000, 106 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 107 .emif_rd_wr_lvl_ctl = 0x00000000, 108 .emif_rd_wr_exec_thresh = 0x00000305 109 }; 110 111 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { 112 .sdram_config_init = 0x61862B32, 113 .sdram_config = 0x61862B32, 114 .sdram_config2 = 0x08000000, 115 .ref_ctrl = 0x0000514C, 116 .ref_ctrl_final = 0x0000144A, 117 .sdram_tim1 = 0xD113781C, 118 .sdram_tim2 = 0x30717FE3, 119 .sdram_tim3 = 0x409F86A8, 120 .read_idle_ctrl = 0x00050000, 121 .zq_config = 0x5007190B, 122 .temp_alert_config = 0x00000000, 123 .emif_ddr_phy_ctlr_1_init = 0x0024400D, 124 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 125 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 126 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, 127 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, 128 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, 129 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, 130 .emif_rd_wr_lvl_rmp_win = 0x00000000, 131 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 132 .emif_rd_wr_lvl_ctl = 0x00000000, 133 .emif_rd_wr_exec_thresh = 0x00000305 134 }; 135 136 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { 137 .sdram_config_init = 0x61862BB2, 138 .sdram_config = 0x61862BB2, 139 .sdram_config2 = 0x00000000, 140 .ref_ctrl = 0x0000514D, 141 .ref_ctrl_final = 0x0000144A, 142 .sdram_tim1 = 0xD1137824, 143 .sdram_tim2 = 0x30B37FE3, 144 .sdram_tim3 = 0x409F8AD8, 145 .read_idle_ctrl = 0x00050000, 146 .zq_config = 0x5007190B, 147 .temp_alert_config = 0x00000000, 148 .emif_ddr_phy_ctlr_1_init = 0x0824400E, 149 .emif_ddr_phy_ctlr_1 = 0x0E24400E, 150 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 151 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, 152 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, 153 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, 154 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, 155 .emif_rd_wr_lvl_rmp_win = 0x00000000, 156 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 157 .emif_rd_wr_lvl_ctl = 0x00000000, 158 .emif_rd_wr_exec_thresh = 0x00000305 159 }; 160 161 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { 162 .sdram_config_init = 0x61851ab2, 163 .sdram_config = 0x61851ab2, 164 .sdram_config2 = 0x08000000, 165 .ref_ctrl = 0x000040F1, 166 .ref_ctrl_final = 0x00001035, 167 .sdram_tim1 = 0xCCCF36B3, 168 .sdram_tim2 = 0x30BF7FDA, 169 .sdram_tim3 = 0x427F8BA8, 170 .read_idle_ctrl = 0x00050000, 171 .zq_config = 0x0007190B, 172 .temp_alert_config = 0x00000000, 173 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 174 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 175 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 176 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 177 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 178 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 179 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 180 .emif_rd_wr_lvl_rmp_win = 0x00000000, 181 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 182 .emif_rd_wr_lvl_ctl = 0x00000000, 183 .emif_rd_wr_exec_thresh = 0x00000305 184 }; 185 186 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { 187 .sdram_config_init = 0x61851B32, 188 .sdram_config = 0x61851B32, 189 .sdram_config2 = 0x08000000, 190 .ref_ctrl = 0x000040F1, 191 .ref_ctrl_final = 0x00001035, 192 .sdram_tim1 = 0xCCCF36B3, 193 .sdram_tim2 = 0x308F7FDA, 194 .sdram_tim3 = 0x427F88A8, 195 .read_idle_ctrl = 0x00050000, 196 .zq_config = 0x0007190B, 197 .temp_alert_config = 0x00000000, 198 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 199 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 200 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 201 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 202 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 203 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 204 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 205 .emif_rd_wr_lvl_rmp_win = 0x00000000, 206 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 207 .emif_rd_wr_lvl_ctl = 0x00000000, 208 .emif_rd_wr_exec_thresh = 0x00000305 209 }; 210 211 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 212 { 213 u64 ram_size; 214 215 ram_size = board_ti_get_emif_size(); 216 217 switch (omap_revision()) { 218 case DRA752_ES1_0: 219 case DRA752_ES1_1: 220 case DRA752_ES2_0: 221 switch (emif_nr) { 222 case 1: 223 if (ram_size > CONFIG_MAX_MEM_MAPPED) 224 *regs = &emif1_ddr3_532_mhz_1cs_2G; 225 else 226 *regs = &emif1_ddr3_532_mhz_1cs; 227 break; 228 case 2: 229 if (ram_size > CONFIG_MAX_MEM_MAPPED) 230 *regs = &emif2_ddr3_532_mhz_1cs_2G; 231 else 232 *regs = &emif2_ddr3_532_mhz_1cs; 233 break; 234 } 235 break; 236 case DRA722_ES1_0: 237 case DRA722_ES2_0: 238 if (ram_size < CONFIG_MAX_MEM_MAPPED) 239 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; 240 else 241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; 242 break; 243 default: 244 *regs = &emif1_ddr3_532_mhz_1cs; 245 } 246 } 247 248 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { 249 .dmm_lisa_map_0 = 0x0, 250 .dmm_lisa_map_1 = 0x80640300, 251 .dmm_lisa_map_2 = 0xC0500220, 252 .dmm_lisa_map_3 = 0xFF020100, 253 .is_ma_present = 0x1 254 }; 255 256 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { 257 .dmm_lisa_map_0 = 0x0, 258 .dmm_lisa_map_1 = 0x0, 259 .dmm_lisa_map_2 = 0x80600100, 260 .dmm_lisa_map_3 = 0xFF020100, 261 .is_ma_present = 0x1 262 }; 263 264 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { 265 .dmm_lisa_map_0 = 0x0, 266 .dmm_lisa_map_1 = 0x0, 267 .dmm_lisa_map_2 = 0x80740300, 268 .dmm_lisa_map_3 = 0xFF020100, 269 .is_ma_present = 0x1 270 }; 271 272 /* 273 * DRA722 EVM EMIF1 2GB CONFIGURATION 274 * EMIF1 4 devices of 512Mb x 8 Micron 275 */ 276 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { 277 .dmm_lisa_map_0 = 0x0, 278 .dmm_lisa_map_1 = 0x0, 279 .dmm_lisa_map_2 = 0x80700100, 280 .dmm_lisa_map_3 = 0xFF020100, 281 .is_ma_present = 0x1 282 }; 283 284 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 285 { 286 u64 ram_size; 287 288 ram_size = board_ti_get_emif_size(); 289 290 switch (omap_revision()) { 291 case DRA752_ES1_0: 292 case DRA752_ES1_1: 293 case DRA752_ES2_0: 294 if (ram_size > CONFIG_MAX_MEM_MAPPED) 295 *dmm_lisa_regs = &lisa_map_dra7_2GB; 296 else 297 *dmm_lisa_regs = &lisa_map_dra7_1536MB; 298 break; 299 case DRA722_ES1_0: 300 case DRA722_ES2_0: 301 default: 302 if (ram_size < CONFIG_MAX_MEM_MAPPED) 303 *dmm_lisa_regs = &lisa_map_2G_x_2; 304 else 305 *dmm_lisa_regs = &lisa_map_2G_x_4; 306 break; 307 } 308 } 309 310 struct vcores_data dra752_volts = { 311 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 312 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 313 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 314 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 315 .mpu.pmic = &tps659038, 316 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 317 318 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 319 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 320 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 321 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 322 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 323 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 324 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 325 .eve.addr = TPS659038_REG_ADDR_SMPS45, 326 .eve.pmic = &tps659038, 327 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 328 329 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 330 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 331 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 332 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 333 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 334 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 335 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 336 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 337 .gpu.pmic = &tps659038, 338 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 339 340 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 341 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 342 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 343 .core.addr = TPS659038_REG_ADDR_SMPS7, 344 .core.pmic = &tps659038, 345 346 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 347 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 348 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 349 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 350 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 351 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 352 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 353 .iva.addr = TPS659038_REG_ADDR_SMPS8, 354 .iva.pmic = &tps659038, 355 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 356 }; 357 358 struct vcores_data dra722_volts = { 359 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM, 360 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM, 361 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 362 .mpu.addr = TPS65917_REG_ADDR_SMPS1, 363 .mpu.pmic = &tps659038, 364 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 365 366 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM, 367 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM, 368 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 369 .core.addr = TPS65917_REG_ADDR_SMPS2, 370 .core.pmic = &tps659038, 371 372 /* 373 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x 374 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. 375 */ 376 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM, 377 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD, 378 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH, 379 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM, 380 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD, 381 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH, 382 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 383 .gpu.addr = TPS65917_REG_ADDR_SMPS3, 384 .gpu.pmic = &tps659038, 385 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 386 387 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM, 388 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD, 389 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH, 390 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM, 391 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD, 392 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH, 393 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 394 .eve.addr = TPS65917_REG_ADDR_SMPS3, 395 .eve.pmic = &tps659038, 396 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 397 398 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM, 399 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD, 400 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH, 401 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM, 402 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD, 403 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH, 404 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 405 .iva.addr = TPS65917_REG_ADDR_SMPS3, 406 .iva.pmic = &tps659038, 407 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 408 }; 409 410 int get_voltrail_opp(int rail_offset) 411 { 412 int opp; 413 414 switch (rail_offset) { 415 case VOLT_MPU: 416 opp = DRA7_MPU_OPP; 417 break; 418 case VOLT_CORE: 419 opp = DRA7_CORE_OPP; 420 break; 421 case VOLT_GPU: 422 opp = DRA7_GPU_OPP; 423 break; 424 case VOLT_EVE: 425 opp = DRA7_DSPEVE_OPP; 426 break; 427 case VOLT_IVA: 428 opp = DRA7_IVA_OPP; 429 break; 430 default: 431 opp = OPP_NOM; 432 } 433 434 return opp; 435 } 436 437 /** 438 * @brief board_init 439 * 440 * @return 0 441 */ 442 int board_init(void) 443 { 444 gpmc_init(); 445 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 446 447 return 0; 448 } 449 450 void dram_init_banksize(void) 451 { 452 u64 ram_size; 453 454 ram_size = board_ti_get_emif_size(); 455 456 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 457 gd->bd->bi_dram[0].size = get_effective_memsize(); 458 if (ram_size > CONFIG_MAX_MEM_MAPPED) { 459 gd->bd->bi_dram[1].start = 0x200000000; 460 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; 461 } 462 } 463 464 int board_late_init(void) 465 { 466 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 467 char *name = "unknown"; 468 469 if (is_dra72x()) { 470 if (board_is_dra72x_revc_or_later()) 471 name = "dra72x-revc"; 472 else 473 name = "dra72x"; 474 } else { 475 name = "dra7xx"; 476 } 477 478 set_board_info_env(name); 479 480 /* 481 * Default FIT boot on HS devices. Non FIT images are not allowed 482 * on HS devices. 483 */ 484 if (get_device_type() == HS_DEVICE) 485 setenv("boot_fit", "1"); 486 487 omap_die_id_serial(); 488 #endif 489 return 0; 490 } 491 492 #ifdef CONFIG_SPL_BUILD 493 void do_board_detect(void) 494 { 495 int rc; 496 497 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 498 CONFIG_EEPROM_CHIP_ADDRESS); 499 if (rc) 500 printf("ti_i2c_eeprom_init failed %d\n", rc); 501 } 502 503 #else 504 505 void do_board_detect(void) 506 { 507 char *bname = NULL; 508 int rc; 509 510 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 511 CONFIG_EEPROM_CHIP_ADDRESS); 512 if (rc) 513 printf("ti_i2c_eeprom_init failed %d\n", rc); 514 515 if (board_is_dra74x_evm()) { 516 bname = "DRA74x EVM"; 517 } else if (board_is_dra72x_evm()) { 518 bname = "DRA72x EVM"; 519 } else { 520 /* If EEPROM is not populated */ 521 if (is_dra72x()) 522 bname = "DRA72x EVM"; 523 else 524 bname = "DRA74x EVM"; 525 } 526 527 if (bname) 528 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 529 "Board: %s REV %s\n", bname, board_ti_get_rev()); 530 } 531 #endif /* CONFIG_SPL_BUILD */ 532 533 void vcores_init(void) 534 { 535 if (board_is_dra74x_evm()) { 536 *omap_vcores = &dra752_volts; 537 } else if (board_is_dra72x_evm()) { 538 *omap_vcores = &dra722_volts; 539 } else { 540 /* If EEPROM is not populated */ 541 if (is_dra72x()) 542 *omap_vcores = &dra722_volts; 543 else 544 *omap_vcores = &dra752_volts; 545 } 546 } 547 548 void set_muxconf_regs(void) 549 { 550 do_set_mux32((*ctrl)->control_padconf_core_base, 551 early_padconf, ARRAY_SIZE(early_padconf)); 552 } 553 554 #ifdef CONFIG_IODELAY_RECALIBRATION 555 void recalibrate_iodelay(void) 556 { 557 struct pad_conf_entry const *pads, *delta_pads = NULL; 558 struct iodelay_cfg_entry const *iodelay; 559 int npads, niodelays, delta_npads = 0; 560 int ret; 561 562 switch (omap_revision()) { 563 case DRA722_ES1_0: 564 case DRA722_ES2_0: 565 pads = dra72x_core_padconf_array_common; 566 npads = ARRAY_SIZE(dra72x_core_padconf_array_common); 567 if (board_is_dra72x_revc_or_later()) { 568 delta_pads = dra72x_rgmii_padconf_array_revc; 569 delta_npads = 570 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); 571 iodelay = dra72_iodelay_cfg_array_revc; 572 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); 573 } else { 574 delta_pads = dra72x_rgmii_padconf_array_revb; 575 delta_npads = 576 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); 577 iodelay = dra72_iodelay_cfg_array_revb; 578 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); 579 } 580 break; 581 case DRA752_ES1_0: 582 case DRA752_ES1_1: 583 pads = dra74x_core_padconf_array; 584 npads = ARRAY_SIZE(dra74x_core_padconf_array); 585 iodelay = dra742_es1_1_iodelay_cfg_array; 586 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 587 break; 588 default: 589 case DRA752_ES2_0: 590 pads = dra74x_core_padconf_array; 591 npads = ARRAY_SIZE(dra74x_core_padconf_array); 592 iodelay = dra742_es2_0_iodelay_cfg_array; 593 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 594 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 595 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 596 RGMII1_ID_MODE_N_MASK); 597 break; 598 } 599 /* Setup I/O isolation */ 600 ret = __recalibrate_iodelay_start(); 601 if (ret) 602 goto err; 603 604 /* Do the muxing here */ 605 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); 606 607 /* Now do the weird minor deltas that should be safe */ 608 if (delta_npads) 609 do_set_mux32((*ctrl)->control_padconf_core_base, 610 delta_pads, delta_npads); 611 612 /* Setup IOdelay configuration */ 613 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); 614 err: 615 /* Closeup.. remove isolation */ 616 __recalibrate_iodelay_end(ret); 617 } 618 #endif 619 620 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 621 int board_mmc_init(bd_t *bis) 622 { 623 omap_mmc_init(0, 0, 0, -1, -1); 624 omap_mmc_init(1, 0, 0, -1, -1); 625 return 0; 626 } 627 #endif 628 629 #ifdef CONFIG_USB_DWC3 630 static struct dwc3_device usb_otg_ss1 = { 631 .maximum_speed = USB_SPEED_SUPER, 632 .base = DRA7_USB_OTG_SS1_BASE, 633 .tx_fifo_resize = false, 634 .index = 0, 635 }; 636 637 static struct dwc3_omap_device usb_otg_ss1_glue = { 638 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 639 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 640 .index = 0, 641 }; 642 643 static struct ti_usb_phy_device usb_phy1_device = { 644 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 645 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 646 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 647 .index = 0, 648 }; 649 650 static struct dwc3_device usb_otg_ss2 = { 651 .maximum_speed = USB_SPEED_SUPER, 652 .base = DRA7_USB_OTG_SS2_BASE, 653 .tx_fifo_resize = false, 654 .index = 1, 655 }; 656 657 static struct dwc3_omap_device usb_otg_ss2_glue = { 658 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 659 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 660 .index = 1, 661 }; 662 663 static struct ti_usb_phy_device usb_phy2_device = { 664 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 665 .index = 1, 666 }; 667 668 int board_usb_init(int index, enum usb_init_type init) 669 { 670 enable_usb_clocks(index); 671 switch (index) { 672 case 0: 673 if (init == USB_INIT_DEVICE) { 674 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 675 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 676 } else { 677 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 678 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 679 } 680 681 ti_usb_phy_uboot_init(&usb_phy1_device); 682 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 683 dwc3_uboot_init(&usb_otg_ss1); 684 break; 685 case 1: 686 if (init == USB_INIT_DEVICE) { 687 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 688 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 689 } else { 690 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 691 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 692 } 693 694 ti_usb_phy_uboot_init(&usb_phy2_device); 695 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 696 dwc3_uboot_init(&usb_otg_ss2); 697 break; 698 default: 699 printf("Invalid Controller Index\n"); 700 } 701 702 return 0; 703 } 704 705 int board_usb_cleanup(int index, enum usb_init_type init) 706 { 707 switch (index) { 708 case 0: 709 case 1: 710 ti_usb_phy_uboot_exit(index); 711 dwc3_uboot_exit(index); 712 dwc3_omap_uboot_exit(index); 713 break; 714 default: 715 printf("Invalid Controller Index\n"); 716 } 717 disable_usb_clocks(index); 718 return 0; 719 } 720 721 int usb_gadget_handle_interrupts(int index) 722 { 723 u32 status; 724 725 status = dwc3_omap_uboot_interrupt_status(index); 726 if (status) 727 dwc3_uboot_handle_interrupt(index); 728 729 return 0; 730 } 731 #endif 732 733 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 734 int spl_start_uboot(void) 735 { 736 /* break into full u-boot on 'c' */ 737 if (serial_tstc() && serial_getc() == 'c') 738 return 1; 739 740 #ifdef CONFIG_SPL_ENV_SUPPORT 741 env_init(); 742 env_relocate_spec(); 743 if (getenv_yesno("boot_os") != 1) 744 return 1; 745 #endif 746 747 return 0; 748 } 749 #endif 750 751 #ifdef CONFIG_DRIVER_TI_CPSW 752 extern u32 *const omap_si_rev; 753 754 static void cpsw_control(int enabled) 755 { 756 /* VTP can be added here */ 757 758 return; 759 } 760 761 static struct cpsw_slave_data cpsw_slaves[] = { 762 { 763 .slave_reg_ofs = 0x208, 764 .sliver_reg_ofs = 0xd80, 765 .phy_addr = 2, 766 }, 767 { 768 .slave_reg_ofs = 0x308, 769 .sliver_reg_ofs = 0xdc0, 770 .phy_addr = 3, 771 }, 772 }; 773 774 static struct cpsw_platform_data cpsw_data = { 775 .mdio_base = CPSW_MDIO_BASE, 776 .cpsw_base = CPSW_BASE, 777 .mdio_div = 0xff, 778 .channels = 8, 779 .cpdma_reg_ofs = 0x800, 780 .slaves = 2, 781 .slave_data = cpsw_slaves, 782 .ale_reg_ofs = 0xd00, 783 .ale_entries = 1024, 784 .host_port_reg_ofs = 0x108, 785 .hw_stats_reg_ofs = 0x900, 786 .bd_ram_ofs = 0x2000, 787 .mac_control = (1 << 5), 788 .control = cpsw_control, 789 .host_port_num = 0, 790 .version = CPSW_CTRL_VERSION_2, 791 }; 792 793 int board_eth_init(bd_t *bis) 794 { 795 int ret; 796 uint8_t mac_addr[6]; 797 uint32_t mac_hi, mac_lo; 798 uint32_t ctrl_val; 799 800 /* try reading mac address from efuse */ 801 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 802 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 803 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 804 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 805 mac_addr[2] = mac_hi & 0xFF; 806 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 807 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 808 mac_addr[5] = mac_lo & 0xFF; 809 810 if (!getenv("ethaddr")) { 811 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 812 813 if (is_valid_ethaddr(mac_addr)) 814 eth_setenv_enetaddr("ethaddr", mac_addr); 815 } 816 817 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 818 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 819 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 820 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 821 mac_addr[2] = mac_hi & 0xFF; 822 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 823 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 824 mac_addr[5] = mac_lo & 0xFF; 825 826 if (!getenv("eth1addr")) { 827 if (is_valid_ethaddr(mac_addr)) 828 eth_setenv_enetaddr("eth1addr", mac_addr); 829 } 830 831 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 832 ctrl_val |= 0x22; 833 writel(ctrl_val, (*ctrl)->control_core_control_io1); 834 835 if (*omap_si_rev == DRA722_ES1_0) 836 cpsw_data.active_slave = 1; 837 838 if (board_is_dra72x_revc_or_later()) { 839 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 840 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 841 } 842 843 ret = cpsw_register(&cpsw_data); 844 if (ret < 0) 845 printf("Error %d registering CPSW switch\n", ret); 846 847 return ret; 848 } 849 #endif 850 851 #ifdef CONFIG_BOARD_EARLY_INIT_F 852 /* VTT regulator enable */ 853 static inline void vtt_regulator_enable(void) 854 { 855 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 856 return; 857 858 /* Do not enable VTT for DRA722 */ 859 if (is_dra72x()) 860 return; 861 862 /* 863 * EVM Rev G and later use gpio7_11 for DDR3 termination. 864 * This is safe enough to do on older revs. 865 */ 866 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 867 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 868 } 869 870 int board_early_init_f(void) 871 { 872 vtt_regulator_enable(); 873 return 0; 874 } 875 #endif 876 877 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 878 int ft_board_setup(void *blob, bd_t *bd) 879 { 880 ft_cpu_setup(blob, bd); 881 882 return 0; 883 } 884 #endif 885 886 #ifdef CONFIG_SPL_LOAD_FIT 887 int board_fit_config_name_match(const char *name) 888 { 889 if (is_dra72x()) { 890 if (board_is_dra72x_revc_or_later()) { 891 if (!strcmp(name, "dra72-evm-revc")) 892 return 0; 893 } else if (!strcmp(name, "dra72-evm")) { 894 return 0; 895 } 896 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { 897 return 0; 898 } 899 900 return -1; 901 } 902 #endif 903 904 #ifdef CONFIG_TI_SECURE_DEVICE 905 void board_fit_image_post_process(void **p_image, size_t *p_size) 906 { 907 secure_boot_verify_image(p_image, p_size); 908 } 909 910 void board_tee_image_process(ulong tee_image, size_t tee_size) 911 { 912 secure_tee_install((u32)tee_image); 913 } 914 915 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 916 #endif 917