1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <linux/string.h> 17 #include <asm/gpio.h> 18 #include <usb.h> 19 #include <linux/usb/gadget.h> 20 #include <asm/omap_common.h> 21 #include <asm/omap_sec_common.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/dra7xx_iodelay.h> 24 #include <asm/emif.h> 25 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/mmc_host_def.h> 27 #include <asm/arch/sata.h> 28 #include <environment.h> 29 #include <dwc3-uboot.h> 30 #include <dwc3-omap-uboot.h> 31 #include <ti-usb-phy-uboot.h> 32 #include <miiphy.h> 33 34 #include "mux_data.h" 35 #include "../common/board_detect.h" 36 37 #define board_is_dra74x_evm() board_ti_is("5777xCPU") 38 #define board_is_dra72x_evm() board_ti_is("DRA72x-T") 39 #define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ 40 (strncmp("H", board_ti_get_rev(), 1) <= 0)) 41 #define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ 42 (strncmp("C", board_ti_get_rev(), 1) <= 0)) 43 #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ 44 board_ti_get_emif2_size() 45 46 #ifdef CONFIG_DRIVER_TI_CPSW 47 #include <cpsw.h> 48 #endif 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 /* GPIO 7_11 */ 53 #define GPIO_DDR_VTT_EN 203 54 55 #define SYSINFO_BOARD_NAME_MAX_LEN 37 56 57 const struct omap_sysinfo sysinfo = { 58 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n" 59 }; 60 61 static const struct emif_regs emif1_ddr3_532_mhz_1cs = { 62 .sdram_config_init = 0x61851ab2, 63 .sdram_config = 0x61851ab2, 64 .sdram_config2 = 0x08000000, 65 .ref_ctrl = 0x000040F1, 66 .ref_ctrl_final = 0x00001035, 67 .sdram_tim1 = 0xCCCF36B3, 68 .sdram_tim2 = 0x308F7FDA, 69 .sdram_tim3 = 0x427F88A8, 70 .read_idle_ctrl = 0x00050000, 71 .zq_config = 0x0007190B, 72 .temp_alert_config = 0x00000000, 73 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 74 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 75 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 76 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 77 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 78 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 79 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 80 .emif_rd_wr_lvl_rmp_win = 0x00000000, 81 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 82 .emif_rd_wr_lvl_ctl = 0x00000000, 83 .emif_rd_wr_exec_thresh = 0x00000305 84 }; 85 86 static const struct emif_regs emif2_ddr3_532_mhz_1cs = { 87 .sdram_config_init = 0x61851B32, 88 .sdram_config = 0x61851B32, 89 .sdram_config2 = 0x08000000, 90 .ref_ctrl = 0x000040F1, 91 .ref_ctrl_final = 0x00001035, 92 .sdram_tim1 = 0xCCCF36B3, 93 .sdram_tim2 = 0x308F7FDA, 94 .sdram_tim3 = 0x427F88A8, 95 .read_idle_ctrl = 0x00050000, 96 .zq_config = 0x0007190B, 97 .temp_alert_config = 0x00000000, 98 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 99 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 100 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 101 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 102 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 103 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 104 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 105 .emif_rd_wr_lvl_rmp_win = 0x00000000, 106 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 107 .emif_rd_wr_lvl_ctl = 0x00000000, 108 .emif_rd_wr_exec_thresh = 0x00000305 109 }; 110 111 static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = { 112 .sdram_config_init = 0x61862B32, 113 .sdram_config = 0x61862B32, 114 .sdram_config2 = 0x08000000, 115 .ref_ctrl = 0x0000514C, 116 .ref_ctrl_final = 0x0000144A, 117 .sdram_tim1 = 0xD113781C, 118 .sdram_tim2 = 0x30717FE3, 119 .sdram_tim3 = 0x409F86A8, 120 .read_idle_ctrl = 0x00050000, 121 .zq_config = 0x5007190B, 122 .temp_alert_config = 0x00000000, 123 .emif_ddr_phy_ctlr_1_init = 0x0024400D, 124 .emif_ddr_phy_ctlr_1 = 0x0E24400D, 125 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 126 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4, 127 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9, 128 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0, 129 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0, 130 .emif_rd_wr_lvl_rmp_win = 0x00000000, 131 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 132 .emif_rd_wr_lvl_ctl = 0x00000000, 133 .emif_rd_wr_exec_thresh = 0x00000305 134 }; 135 136 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = { 137 .sdram_config_init = 0x61862BB2, 138 .sdram_config = 0x61862BB2, 139 .sdram_config2 = 0x00000000, 140 .ref_ctrl = 0x0000514D, 141 .ref_ctrl_final = 0x0000144A, 142 .sdram_tim1 = 0xD1137824, 143 .sdram_tim2 = 0x30B37FE3, 144 .sdram_tim3 = 0x409F8AD8, 145 .read_idle_ctrl = 0x00050000, 146 .zq_config = 0x5007190B, 147 .temp_alert_config = 0x00000000, 148 .emif_ddr_phy_ctlr_1_init = 0x0824400E, 149 .emif_ddr_phy_ctlr_1 = 0x0E24400E, 150 .emif_ddr_ext_phy_ctrl_1 = 0x04040100, 151 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F, 152 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2, 153 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8, 154 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8, 155 .emif_rd_wr_lvl_rmp_win = 0x00000000, 156 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 157 .emif_rd_wr_lvl_ctl = 0x00000000, 158 .emif_rd_wr_exec_thresh = 0x00000305 159 }; 160 161 const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = { 162 .sdram_config_init = 0x61851ab2, 163 .sdram_config = 0x61851ab2, 164 .sdram_config2 = 0x08000000, 165 .ref_ctrl = 0x000040F1, 166 .ref_ctrl_final = 0x00001035, 167 .sdram_tim1 = 0xCCCF36B3, 168 .sdram_tim2 = 0x30BF7FDA, 169 .sdram_tim3 = 0x427F8BA8, 170 .read_idle_ctrl = 0x00050000, 171 .zq_config = 0x0007190B, 172 .temp_alert_config = 0x00000000, 173 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 174 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 175 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 176 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 177 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 178 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 179 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 180 .emif_rd_wr_lvl_rmp_win = 0x00000000, 181 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 182 .emif_rd_wr_lvl_ctl = 0x00000000, 183 .emif_rd_wr_exec_thresh = 0x00000305 184 }; 185 186 const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = { 187 .sdram_config_init = 0x61851B32, 188 .sdram_config = 0x61851B32, 189 .sdram_config2 = 0x08000000, 190 .ref_ctrl = 0x000040F1, 191 .ref_ctrl_final = 0x00001035, 192 .sdram_tim1 = 0xCCCF36B3, 193 .sdram_tim2 = 0x308F7FDA, 194 .sdram_tim3 = 0x427F88A8, 195 .read_idle_ctrl = 0x00050000, 196 .zq_config = 0x0007190B, 197 .temp_alert_config = 0x00000000, 198 .emif_ddr_phy_ctlr_1_init = 0x0024400B, 199 .emif_ddr_phy_ctlr_1 = 0x0E24400B, 200 .emif_ddr_ext_phy_ctrl_1 = 0x10040100, 201 .emif_ddr_ext_phy_ctrl_2 = 0x00910091, 202 .emif_ddr_ext_phy_ctrl_3 = 0x00950095, 203 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B, 204 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, 205 .emif_rd_wr_lvl_rmp_win = 0x00000000, 206 .emif_rd_wr_lvl_rmp_ctl = 0x80000000, 207 .emif_rd_wr_lvl_ctl = 0x00000000, 208 .emif_rd_wr_exec_thresh = 0x00000305 209 }; 210 211 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) 212 { 213 u64 ram_size; 214 215 ram_size = board_ti_get_emif_size(); 216 217 switch (omap_revision()) { 218 case DRA752_ES1_0: 219 case DRA752_ES1_1: 220 case DRA752_ES2_0: 221 switch (emif_nr) { 222 case 1: 223 if (ram_size > CONFIG_MAX_MEM_MAPPED) 224 *regs = &emif1_ddr3_532_mhz_1cs_2G; 225 else 226 *regs = &emif1_ddr3_532_mhz_1cs; 227 break; 228 case 2: 229 if (ram_size > CONFIG_MAX_MEM_MAPPED) 230 *regs = &emif2_ddr3_532_mhz_1cs_2G; 231 else 232 *regs = &emif2_ddr3_532_mhz_1cs; 233 break; 234 } 235 break; 236 case DRA722_ES1_0: 237 case DRA722_ES2_0: 238 if (ram_size < CONFIG_MAX_MEM_MAPPED) 239 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; 240 else 241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; 242 break; 243 default: 244 *regs = &emif1_ddr3_532_mhz_1cs; 245 } 246 } 247 248 static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = { 249 .dmm_lisa_map_0 = 0x0, 250 .dmm_lisa_map_1 = 0x80640300, 251 .dmm_lisa_map_2 = 0xC0500220, 252 .dmm_lisa_map_3 = 0xFF020100, 253 .is_ma_present = 0x1 254 }; 255 256 static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { 257 .dmm_lisa_map_0 = 0x0, 258 .dmm_lisa_map_1 = 0x0, 259 .dmm_lisa_map_2 = 0x80600100, 260 .dmm_lisa_map_3 = 0xFF020100, 261 .is_ma_present = 0x1 262 }; 263 264 const struct dmm_lisa_map_regs lisa_map_dra7_2GB = { 265 .dmm_lisa_map_0 = 0x0, 266 .dmm_lisa_map_1 = 0x0, 267 .dmm_lisa_map_2 = 0x80740300, 268 .dmm_lisa_map_3 = 0xFF020100, 269 .is_ma_present = 0x1 270 }; 271 272 /* 273 * DRA722 EVM EMIF1 2GB CONFIGURATION 274 * EMIF1 4 devices of 512Mb x 8 Micron 275 */ 276 const struct dmm_lisa_map_regs lisa_map_2G_x_4 = { 277 .dmm_lisa_map_0 = 0x0, 278 .dmm_lisa_map_1 = 0x0, 279 .dmm_lisa_map_2 = 0x80700100, 280 .dmm_lisa_map_3 = 0xFF020100, 281 .is_ma_present = 0x1 282 }; 283 284 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) 285 { 286 u64 ram_size; 287 288 ram_size = board_ti_get_emif_size(); 289 290 switch (omap_revision()) { 291 case DRA752_ES1_0: 292 case DRA752_ES1_1: 293 case DRA752_ES2_0: 294 if (ram_size > CONFIG_MAX_MEM_MAPPED) 295 *dmm_lisa_regs = &lisa_map_dra7_2GB; 296 else 297 *dmm_lisa_regs = &lisa_map_dra7_1536MB; 298 break; 299 case DRA722_ES1_0: 300 case DRA722_ES2_0: 301 default: 302 if (ram_size < CONFIG_MAX_MEM_MAPPED) 303 *dmm_lisa_regs = &lisa_map_2G_x_2; 304 else 305 *dmm_lisa_regs = &lisa_map_2G_x_4; 306 break; 307 } 308 } 309 310 struct vcores_data dra752_volts = { 311 .mpu.value = VDD_MPU_DRA7, 312 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, 313 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 314 .mpu.addr = TPS659038_REG_ADDR_SMPS12, 315 .mpu.pmic = &tps659038, 316 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 317 318 .eve.value = VDD_EVE_DRA7, 319 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, 320 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 321 .eve.addr = TPS659038_REG_ADDR_SMPS45, 322 .eve.pmic = &tps659038, 323 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 324 325 .gpu.value = VDD_GPU_DRA7, 326 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, 327 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 328 .gpu.addr = TPS659038_REG_ADDR_SMPS6, 329 .gpu.pmic = &tps659038, 330 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 331 332 .core.value = VDD_CORE_DRA7, 333 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, 334 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 335 .core.addr = TPS659038_REG_ADDR_SMPS7, 336 .core.pmic = &tps659038, 337 338 .iva.value = VDD_IVA_DRA7, 339 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, 340 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 341 .iva.addr = TPS659038_REG_ADDR_SMPS8, 342 .iva.pmic = &tps659038, 343 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 344 }; 345 346 struct vcores_data dra722_volts = { 347 .mpu.value = VDD_MPU_DRA7, 348 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU, 349 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 350 .mpu.addr = TPS65917_REG_ADDR_SMPS1, 351 .mpu.pmic = &tps659038, 352 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 353 354 .core.value = VDD_CORE_DRA7, 355 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE, 356 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, 357 .core.addr = TPS65917_REG_ADDR_SMPS2, 358 .core.pmic = &tps659038, 359 360 /* 361 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x 362 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM. 363 */ 364 .gpu.value = VDD_GPU_DRA7, 365 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU, 366 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, 367 .gpu.addr = TPS65917_REG_ADDR_SMPS3, 368 .gpu.pmic = &tps659038, 369 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK, 370 371 .eve.value = VDD_EVE_DRA7, 372 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE, 373 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, 374 .eve.addr = TPS65917_REG_ADDR_SMPS3, 375 .eve.pmic = &tps659038, 376 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK, 377 378 .iva.value = VDD_IVA_DRA7, 379 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA, 380 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, 381 .iva.addr = TPS65917_REG_ADDR_SMPS3, 382 .iva.pmic = &tps659038, 383 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK, 384 }; 385 386 /** 387 * @brief board_init 388 * 389 * @return 0 390 */ 391 int board_init(void) 392 { 393 gpmc_init(); 394 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 395 396 return 0; 397 } 398 399 void dram_init_banksize(void) 400 { 401 u64 ram_size; 402 403 ram_size = board_ti_get_emif_size(); 404 405 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 406 gd->bd->bi_dram[0].size = get_effective_memsize(); 407 if (ram_size > CONFIG_MAX_MEM_MAPPED) { 408 gd->bd->bi_dram[1].start = 0x200000000; 409 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; 410 } 411 } 412 413 int board_late_init(void) 414 { 415 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 416 char *name = "unknown"; 417 418 if (is_dra72x()) { 419 if (board_is_dra72x_revc_or_later()) 420 name = "dra72x-revc"; 421 else 422 name = "dra72x"; 423 } else { 424 name = "dra7xx"; 425 } 426 427 set_board_info_env(name); 428 429 /* 430 * Default FIT boot on HS devices. Non FIT images are not allowed 431 * on HS devices. 432 */ 433 if (get_device_type() == HS_DEVICE) 434 setenv("boot_fit", "1"); 435 436 omap_die_id_serial(); 437 #endif 438 return 0; 439 } 440 441 #ifdef CONFIG_SPL_BUILD 442 void do_board_detect(void) 443 { 444 int rc; 445 446 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 447 CONFIG_EEPROM_CHIP_ADDRESS); 448 if (rc) 449 printf("ti_i2c_eeprom_init failed %d\n", rc); 450 } 451 452 #else 453 454 void do_board_detect(void) 455 { 456 char *bname = NULL; 457 int rc; 458 459 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS, 460 CONFIG_EEPROM_CHIP_ADDRESS); 461 if (rc) 462 printf("ti_i2c_eeprom_init failed %d\n", rc); 463 464 if (board_is_dra74x_evm()) { 465 bname = "DRA74x EVM"; 466 } else if (board_is_dra72x_evm()) { 467 bname = "DRA72x EVM"; 468 } else { 469 /* If EEPROM is not populated */ 470 if (is_dra72x()) 471 bname = "DRA72x EVM"; 472 else 473 bname = "DRA74x EVM"; 474 } 475 476 if (bname) 477 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN, 478 "Board: %s REV %s\n", bname, board_ti_get_rev()); 479 } 480 #endif /* CONFIG_SPL_BUILD */ 481 482 void vcores_init(void) 483 { 484 if (board_is_dra74x_evm()) { 485 *omap_vcores = &dra752_volts; 486 } else if (board_is_dra72x_evm()) { 487 *omap_vcores = &dra722_volts; 488 } else { 489 /* If EEPROM is not populated */ 490 if (is_dra72x()) 491 *omap_vcores = &dra722_volts; 492 else 493 *omap_vcores = &dra752_volts; 494 } 495 } 496 497 void set_muxconf_regs(void) 498 { 499 do_set_mux32((*ctrl)->control_padconf_core_base, 500 early_padconf, ARRAY_SIZE(early_padconf)); 501 } 502 503 #ifdef CONFIG_IODELAY_RECALIBRATION 504 void recalibrate_iodelay(void) 505 { 506 struct pad_conf_entry const *pads, *delta_pads = NULL; 507 struct iodelay_cfg_entry const *iodelay; 508 int npads, niodelays, delta_npads = 0; 509 int ret; 510 511 switch (omap_revision()) { 512 case DRA722_ES1_0: 513 case DRA722_ES2_0: 514 pads = dra72x_core_padconf_array_common; 515 npads = ARRAY_SIZE(dra72x_core_padconf_array_common); 516 if (board_is_dra72x_revc_or_later()) { 517 delta_pads = dra72x_rgmii_padconf_array_revc; 518 delta_npads = 519 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc); 520 iodelay = dra72_iodelay_cfg_array_revc; 521 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc); 522 } else { 523 delta_pads = dra72x_rgmii_padconf_array_revb; 524 delta_npads = 525 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb); 526 iodelay = dra72_iodelay_cfg_array_revb; 527 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb); 528 } 529 break; 530 case DRA752_ES1_0: 531 case DRA752_ES1_1: 532 pads = dra74x_core_padconf_array; 533 npads = ARRAY_SIZE(dra74x_core_padconf_array); 534 iodelay = dra742_es1_1_iodelay_cfg_array; 535 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array); 536 break; 537 default: 538 case DRA752_ES2_0: 539 pads = dra74x_core_padconf_array; 540 npads = ARRAY_SIZE(dra74x_core_padconf_array); 541 iodelay = dra742_es2_0_iodelay_cfg_array; 542 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array); 543 /* Setup port1 and port2 for rgmii with 'no-id' mode */ 544 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK | 545 RGMII1_ID_MODE_N_MASK); 546 break; 547 } 548 /* Setup I/O isolation */ 549 ret = __recalibrate_iodelay_start(); 550 if (ret) 551 goto err; 552 553 /* Do the muxing here */ 554 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads); 555 556 /* Now do the weird minor deltas that should be safe */ 557 if (delta_npads) 558 do_set_mux32((*ctrl)->control_padconf_core_base, 559 delta_pads, delta_npads); 560 561 /* Setup IOdelay configuration */ 562 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); 563 err: 564 /* Closeup.. remove isolation */ 565 __recalibrate_iodelay_end(ret); 566 } 567 #endif 568 569 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 570 int board_mmc_init(bd_t *bis) 571 { 572 omap_mmc_init(0, 0, 0, -1, -1); 573 omap_mmc_init(1, 0, 0, -1, -1); 574 return 0; 575 } 576 #endif 577 578 #ifdef CONFIG_USB_DWC3 579 static struct dwc3_device usb_otg_ss1 = { 580 .maximum_speed = USB_SPEED_SUPER, 581 .base = DRA7_USB_OTG_SS1_BASE, 582 .tx_fifo_resize = false, 583 .index = 0, 584 }; 585 586 static struct dwc3_omap_device usb_otg_ss1_glue = { 587 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 588 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 589 .index = 0, 590 }; 591 592 static struct ti_usb_phy_device usb_phy1_device = { 593 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 594 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 595 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 596 .index = 0, 597 }; 598 599 static struct dwc3_device usb_otg_ss2 = { 600 .maximum_speed = USB_SPEED_SUPER, 601 .base = DRA7_USB_OTG_SS2_BASE, 602 .tx_fifo_resize = false, 603 .index = 1, 604 }; 605 606 static struct dwc3_omap_device usb_otg_ss2_glue = { 607 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 608 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 609 .index = 1, 610 }; 611 612 static struct ti_usb_phy_device usb_phy2_device = { 613 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 614 .index = 1, 615 }; 616 617 int board_usb_init(int index, enum usb_init_type init) 618 { 619 enable_usb_clocks(index); 620 switch (index) { 621 case 0: 622 if (init == USB_INIT_DEVICE) { 623 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 624 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 625 } else { 626 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 627 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 628 } 629 630 ti_usb_phy_uboot_init(&usb_phy1_device); 631 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 632 dwc3_uboot_init(&usb_otg_ss1); 633 break; 634 case 1: 635 if (init == USB_INIT_DEVICE) { 636 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 637 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 638 } else { 639 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 640 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 641 } 642 643 ti_usb_phy_uboot_init(&usb_phy2_device); 644 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 645 dwc3_uboot_init(&usb_otg_ss2); 646 break; 647 default: 648 printf("Invalid Controller Index\n"); 649 } 650 651 return 0; 652 } 653 654 int board_usb_cleanup(int index, enum usb_init_type init) 655 { 656 switch (index) { 657 case 0: 658 case 1: 659 ti_usb_phy_uboot_exit(index); 660 dwc3_uboot_exit(index); 661 dwc3_omap_uboot_exit(index); 662 break; 663 default: 664 printf("Invalid Controller Index\n"); 665 } 666 disable_usb_clocks(index); 667 return 0; 668 } 669 670 int usb_gadget_handle_interrupts(int index) 671 { 672 u32 status; 673 674 status = dwc3_omap_uboot_interrupt_status(index); 675 if (status) 676 dwc3_uboot_handle_interrupt(index); 677 678 return 0; 679 } 680 #endif 681 682 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 683 int spl_start_uboot(void) 684 { 685 /* break into full u-boot on 'c' */ 686 if (serial_tstc() && serial_getc() == 'c') 687 return 1; 688 689 #ifdef CONFIG_SPL_ENV_SUPPORT 690 env_init(); 691 env_relocate_spec(); 692 if (getenv_yesno("boot_os") != 1) 693 return 1; 694 #endif 695 696 return 0; 697 } 698 #endif 699 700 #ifdef CONFIG_DRIVER_TI_CPSW 701 extern u32 *const omap_si_rev; 702 703 static void cpsw_control(int enabled) 704 { 705 /* VTP can be added here */ 706 707 return; 708 } 709 710 static struct cpsw_slave_data cpsw_slaves[] = { 711 { 712 .slave_reg_ofs = 0x208, 713 .sliver_reg_ofs = 0xd80, 714 .phy_addr = 2, 715 }, 716 { 717 .slave_reg_ofs = 0x308, 718 .sliver_reg_ofs = 0xdc0, 719 .phy_addr = 3, 720 }, 721 }; 722 723 static struct cpsw_platform_data cpsw_data = { 724 .mdio_base = CPSW_MDIO_BASE, 725 .cpsw_base = CPSW_BASE, 726 .mdio_div = 0xff, 727 .channels = 8, 728 .cpdma_reg_ofs = 0x800, 729 .slaves = 2, 730 .slave_data = cpsw_slaves, 731 .ale_reg_ofs = 0xd00, 732 .ale_entries = 1024, 733 .host_port_reg_ofs = 0x108, 734 .hw_stats_reg_ofs = 0x900, 735 .bd_ram_ofs = 0x2000, 736 .mac_control = (1 << 5), 737 .control = cpsw_control, 738 .host_port_num = 0, 739 .version = CPSW_CTRL_VERSION_2, 740 }; 741 742 int board_eth_init(bd_t *bis) 743 { 744 int ret; 745 uint8_t mac_addr[6]; 746 uint32_t mac_hi, mac_lo; 747 uint32_t ctrl_val; 748 749 /* try reading mac address from efuse */ 750 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 751 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 752 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 753 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 754 mac_addr[2] = mac_hi & 0xFF; 755 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 756 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 757 mac_addr[5] = mac_lo & 0xFF; 758 759 if (!getenv("ethaddr")) { 760 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 761 762 if (is_valid_ethaddr(mac_addr)) 763 eth_setenv_enetaddr("ethaddr", mac_addr); 764 } 765 766 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 767 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 768 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 769 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 770 mac_addr[2] = mac_hi & 0xFF; 771 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 772 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 773 mac_addr[5] = mac_lo & 0xFF; 774 775 if (!getenv("eth1addr")) { 776 if (is_valid_ethaddr(mac_addr)) 777 eth_setenv_enetaddr("eth1addr", mac_addr); 778 } 779 780 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 781 ctrl_val |= 0x22; 782 writel(ctrl_val, (*ctrl)->control_core_control_io1); 783 784 if (*omap_si_rev == DRA722_ES1_0) 785 cpsw_data.active_slave = 1; 786 787 if (board_is_dra72x_revc_or_later()) { 788 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 789 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; 790 } 791 792 ret = cpsw_register(&cpsw_data); 793 if (ret < 0) 794 printf("Error %d registering CPSW switch\n", ret); 795 796 return ret; 797 } 798 #endif 799 800 #ifdef CONFIG_BOARD_EARLY_INIT_F 801 /* VTT regulator enable */ 802 static inline void vtt_regulator_enable(void) 803 { 804 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 805 return; 806 807 /* Do not enable VTT for DRA722 */ 808 if (is_dra72x()) 809 return; 810 811 /* 812 * EVM Rev G and later use gpio7_11 for DDR3 termination. 813 * This is safe enough to do on older revs. 814 */ 815 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 816 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 817 } 818 819 int board_early_init_f(void) 820 { 821 vtt_regulator_enable(); 822 return 0; 823 } 824 #endif 825 826 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 827 int ft_board_setup(void *blob, bd_t *bd) 828 { 829 ft_cpu_setup(blob, bd); 830 831 return 0; 832 } 833 #endif 834 835 #ifdef CONFIG_SPL_LOAD_FIT 836 int board_fit_config_name_match(const char *name) 837 { 838 if (is_dra72x()) { 839 if (board_is_dra72x_revc_or_later()) { 840 if (!strcmp(name, "dra72-evm-revc")) 841 return 0; 842 } else if (!strcmp(name, "dra72-evm")) { 843 return 0; 844 } 845 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { 846 return 0; 847 } 848 849 return -1; 850 } 851 #endif 852 853 #ifdef CONFIG_TI_SECURE_DEVICE 854 void board_fit_image_post_process(void **p_image, size_t *p_size) 855 { 856 secure_boot_verify_image(p_image, p_size); 857 } 858 #endif 859