10a0e4badSJean-Christophe PLAGNIOL-VILLARD /* 275c57a35STom Rini * (C) Copyright 2004-2011 30a0e4badSJean-Christophe PLAGNIOL-VILLARD * Texas Instruments, <www.ti.com> 40a0e4badSJean-Christophe PLAGNIOL-VILLARD * 50a0e4badSJean-Christophe PLAGNIOL-VILLARD * Author : 60a0e4badSJean-Christophe PLAGNIOL-VILLARD * Sunil Kumar <sunilsaini05@gmail.com> 70a0e4badSJean-Christophe PLAGNIOL-VILLARD * Shashi Ranjan <shashiranjanmca05@gmail.com> 80a0e4badSJean-Christophe PLAGNIOL-VILLARD * 90a0e4badSJean-Christophe PLAGNIOL-VILLARD * Derived from Beagle Board and 3430 SDP code by 100a0e4badSJean-Christophe PLAGNIOL-VILLARD * Richard Woodruff <r-woodruff2@ti.com> 110a0e4badSJean-Christophe PLAGNIOL-VILLARD * Syed Mohammed Khasim <khasim@ti.com> 120a0e4badSJean-Christophe PLAGNIOL-VILLARD * 130a0e4badSJean-Christophe PLAGNIOL-VILLARD * 140a0e4badSJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 150a0e4badSJean-Christophe PLAGNIOL-VILLARD * project. 160a0e4badSJean-Christophe PLAGNIOL-VILLARD * 170a0e4badSJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 180a0e4badSJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 190a0e4badSJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 200a0e4badSJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 210a0e4badSJean-Christophe PLAGNIOL-VILLARD * 220a0e4badSJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 230a0e4badSJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 240a0e4badSJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 250a0e4badSJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 260a0e4badSJean-Christophe PLAGNIOL-VILLARD * 270a0e4badSJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 280a0e4badSJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 290a0e4badSJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 300a0e4badSJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 310a0e4badSJean-Christophe PLAGNIOL-VILLARD */ 320a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 3370d8c944SJason Kridner #ifdef CONFIG_STATUS_LED 3470d8c944SJason Kridner #include <status_led.h> 3570d8c944SJason Kridner #endif 360a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <twl4030.h> 3775c57a35STom Rini #include <linux/mtd/nand.h> 380a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h> 390cd31144SSteve Sakoman #include <asm/arch/mmc_host_def.h> 400a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/mux.h> 4175c57a35STom Rini #include <asm/arch/mem.h> 420a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/sys_proto.h> 4384c3b631SSanjeev Premi #include <asm/gpio.h> 440a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/mach-types.h> 450a0e4badSJean-Christophe PLAGNIOL-VILLARD #include "beagle.h" 46f835ea71SJason Kridner #include <command.h> 470a0e4badSJean-Christophe PLAGNIOL-VILLARD 4843b62393SGovindraj.R #ifdef CONFIG_USB_EHCI 4943b62393SGovindraj.R #include <usb.h> 5043b62393SGovindraj.R #include <asm/ehci-omap.h> 5143b62393SGovindraj.R #endif 5243b62393SGovindraj.R 53d90859a6SAlexander Holler #define pr_debug(fmt, args...) debug(fmt, ##args) 54d90859a6SAlexander Holler 55ca5f80aeSKoen Kooi #define TWL4030_I2C_BUS 0 56ca5f80aeSKoen Kooi #define EXPANSION_EEPROM_I2C_BUS 1 57ca5f80aeSKoen Kooi #define EXPANSION_EEPROM_I2C_ADDRESS 0x50 58ca5f80aeSKoen Kooi 59ca5f80aeSKoen Kooi #define TINCANTOOLS_ZIPPY 0x01000100 60ca5f80aeSKoen Kooi #define TINCANTOOLS_ZIPPY2 0x02000100 61ca5f80aeSKoen Kooi #define TINCANTOOLS_TRAINER 0x04000100 62ca5f80aeSKoen Kooi #define TINCANTOOLS_SHOWDOG 0x03000100 63ca5f80aeSKoen Kooi #define KBADC_BEAGLEFPGA 0x01000600 64ee8485fdSKoen Kooi #define LW_BEAGLETOUCH 0x01000700 65ee8485fdSKoen Kooi #define BRAINMUX_LCDOG 0x01000800 66ee8485fdSKoen Kooi #define BRAINMUX_LCDOGTOUCH 0x02000800 67ee8485fdSKoen Kooi #define BBTOYS_WIFI 0x01000B00 68ee8485fdSKoen Kooi #define BBTOYS_VGA 0x02000B00 69ee8485fdSKoen Kooi #define BBTOYS_LCD 0x03000B00 706cce5504SPeter Meerwald #define BCT_BRETTL3 0x01000F00 71ca5f80aeSKoen Kooi #define BEAGLE_NO_EEPROM 0xffffffff 72ca5f80aeSKoen Kooi 7329565326SJohn Rigby DECLARE_GLOBAL_DATA_PTR; 7429565326SJohn Rigby 75ca5f80aeSKoen Kooi static struct { 76ca5f80aeSKoen Kooi unsigned int device_vendor; 77ca5f80aeSKoen Kooi unsigned char revision; 78ca5f80aeSKoen Kooi unsigned char content; 79ca5f80aeSKoen Kooi char fab_revision[8]; 80ca5f80aeSKoen Kooi char env_var[16]; 81ca5f80aeSKoen Kooi char env_setting[64]; 82ca5f80aeSKoen Kooi } expansion_config; 83ca5f80aeSKoen Kooi 840a0e4badSJean-Christophe PLAGNIOL-VILLARD /* 850a0e4badSJean-Christophe PLAGNIOL-VILLARD * Routine: board_init 860a0e4badSJean-Christophe PLAGNIOL-VILLARD * Description: Early hardware init. 870a0e4badSJean-Christophe PLAGNIOL-VILLARD */ 880a0e4badSJean-Christophe PLAGNIOL-VILLARD int board_init(void) 890a0e4badSJean-Christophe PLAGNIOL-VILLARD { 900a0e4badSJean-Christophe PLAGNIOL-VILLARD gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 910a0e4badSJean-Christophe PLAGNIOL-VILLARD /* board id for Linux */ 920a0e4badSJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE; 930a0e4badSJean-Christophe PLAGNIOL-VILLARD /* boot param addr */ 940a0e4badSJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 950a0e4badSJean-Christophe PLAGNIOL-VILLARD 9670d8c944SJason Kridner #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) 9770d8c944SJason Kridner status_led_set (STATUS_LED_BOOT, STATUS_LED_ON); 9870d8c944SJason Kridner #endif 9970d8c944SJason Kridner 1000a0e4badSJean-Christophe PLAGNIOL-VILLARD return 0; 1010a0e4badSJean-Christophe PLAGNIOL-VILLARD } 1020a0e4badSJean-Christophe PLAGNIOL-VILLARD 1030a0e4badSJean-Christophe PLAGNIOL-VILLARD /* 10406b95bd5SSteve Sakoman * Routine: get_board_revision 10506b95bd5SSteve Sakoman * Description: Detect if we are running on a Beagle revision Ax/Bx, 10608cbba2aSSteve Sakoman * C1/2/3, C4 or xM. This can be done by reading 10706b95bd5SSteve Sakoman * the level of GPIO173, GPIO172 and GPIO171. This should 10806b95bd5SSteve Sakoman * result in 10906b95bd5SSteve Sakoman * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx 11006b95bd5SSteve Sakoman * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 11106b95bd5SSteve Sakoman * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 11208cbba2aSSteve Sakoman * GPIO173, GPIO172, GPIO171: 0 0 0 => xM 1130a0e4badSJean-Christophe PLAGNIOL-VILLARD */ 11406b95bd5SSteve Sakoman int get_board_revision(void) 1150a0e4badSJean-Christophe PLAGNIOL-VILLARD { 11606b95bd5SSteve Sakoman int revision; 1170a0e4badSJean-Christophe PLAGNIOL-VILLARD 11884c3b631SSanjeev Premi if (!gpio_request(171, "") && 11984c3b631SSanjeev Premi !gpio_request(172, "") && 12084c3b631SSanjeev Premi !gpio_request(173, "")) { 1210a0e4badSJean-Christophe PLAGNIOL-VILLARD 12284c3b631SSanjeev Premi gpio_direction_input(171); 12384c3b631SSanjeev Premi gpio_direction_input(172); 12484c3b631SSanjeev Premi gpio_direction_input(173); 1250a0e4badSJean-Christophe PLAGNIOL-VILLARD 12684c3b631SSanjeev Premi revision = gpio_get_value(173) << 2 | 12784c3b631SSanjeev Premi gpio_get_value(172) << 1 | 12884c3b631SSanjeev Premi gpio_get_value(171); 12906b95bd5SSteve Sakoman } else { 13006b95bd5SSteve Sakoman printf("Error: unable to acquire board revision GPIOs\n"); 13106b95bd5SSteve Sakoman revision = -1; 1320a0e4badSJean-Christophe PLAGNIOL-VILLARD } 1330a0e4badSJean-Christophe PLAGNIOL-VILLARD 13406b95bd5SSteve Sakoman return revision; 1350a0e4badSJean-Christophe PLAGNIOL-VILLARD } 1360a0e4badSJean-Christophe PLAGNIOL-VILLARD 13775c57a35STom Rini #ifdef CONFIG_SPL_BUILD 13875c57a35STom Rini /* 13975c57a35STom Rini * Routine: get_board_mem_timings 14075c57a35STom Rini * Description: If we use SPL then there is no x-loader nor config header 14175c57a35STom Rini * so we have to setup the DDR timings ourself on both banks. 14275c57a35STom Rini */ 14375c57a35STom Rini void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, 14475c57a35STom Rini u32 *mr) 14575c57a35STom Rini { 14675c57a35STom Rini int pop_mfr, pop_id; 14775c57a35STom Rini 14875c57a35STom Rini /* 14975c57a35STom Rini * We need to identify what PoP memory is on the board so that 15075c57a35STom Rini * we know what timings to use. If we can't identify it then 15175c57a35STom Rini * we know it's an xM. To map the ID values please see nand_ids.c 15275c57a35STom Rini */ 15375c57a35STom Rini identify_nand_chip(&pop_mfr, &pop_id); 15475c57a35STom Rini 15575c57a35STom Rini *mr = MICRON_V_MR_165; 15675c57a35STom Rini switch (get_board_revision()) { 15775c57a35STom Rini case REVISION_C4: 15875c57a35STom Rini if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) { 15975c57a35STom Rini /* 512MB DDR */ 16075c57a35STom Rini *mcfg = NUMONYX_V_MCFG_165(512 << 20); 16175c57a35STom Rini *ctrla = NUMONYX_V_ACTIMA_165; 16275c57a35STom Rini *ctrlb = NUMONYX_V_ACTIMB_165; 16375c57a35STom Rini *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 16475c57a35STom Rini break; 165223b8aa4Srobertcnelson@gmail.com } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) { 166223b8aa4Srobertcnelson@gmail.com /* Beagleboard Rev C4, 512MB Nand/256MB DDR*/ 167223b8aa4Srobertcnelson@gmail.com *mcfg = MICRON_V_MCFG_165(128 << 20); 168223b8aa4Srobertcnelson@gmail.com *ctrla = MICRON_V_ACTIMA_165; 169223b8aa4Srobertcnelson@gmail.com *ctrlb = MICRON_V_ACTIMB_165; 170223b8aa4Srobertcnelson@gmail.com *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 171223b8aa4Srobertcnelson@gmail.com break; 17275c57a35STom Rini } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) { 17375c57a35STom Rini /* Beagleboard Rev C5, 256MB DDR */ 17475c57a35STom Rini *mcfg = MICRON_V_MCFG_200(256 << 20); 17575c57a35STom Rini *ctrla = MICRON_V_ACTIMA_200; 17675c57a35STom Rini *ctrlb = MICRON_V_ACTIMB_200; 17775c57a35STom Rini *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 17875c57a35STom Rini break; 17975c57a35STom Rini } 18075c57a35STom Rini case REVISION_XM_A: 18175c57a35STom Rini case REVISION_XM_B: 18275c57a35STom Rini case REVISION_XM_C: 18375c57a35STom Rini if (pop_mfr == 0) { 18475c57a35STom Rini /* 256MB DDR */ 18575c57a35STom Rini *mcfg = MICRON_V_MCFG_200(256 << 20); 18675c57a35STom Rini *ctrla = MICRON_V_ACTIMA_200; 18775c57a35STom Rini *ctrlb = MICRON_V_ACTIMB_200; 18875c57a35STom Rini *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 18975c57a35STom Rini } else { 19075c57a35STom Rini /* 512MB DDR */ 19175c57a35STom Rini *mcfg = NUMONYX_V_MCFG_165(512 << 20); 19275c57a35STom Rini *ctrla = NUMONYX_V_ACTIMA_165; 19375c57a35STom Rini *ctrlb = NUMONYX_V_ACTIMB_165; 19475c57a35STom Rini *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 19575c57a35STom Rini } 19675c57a35STom Rini break; 19775c57a35STom Rini default: 19875c57a35STom Rini /* Assume 128MB and Micron/165MHz timings to be safe */ 19975c57a35STom Rini *mcfg = MICRON_V_MCFG_165(128 << 20); 20075c57a35STom Rini *ctrla = MICRON_V_ACTIMA_165; 20175c57a35STom Rini *ctrlb = MICRON_V_ACTIMB_165; 20275c57a35STom Rini *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 20375c57a35STom Rini } 20475c57a35STom Rini } 20575c57a35STom Rini #endif 20675c57a35STom Rini 2070a0e4badSJean-Christophe PLAGNIOL-VILLARD /* 208ca5f80aeSKoen Kooi * Routine: get_expansion_id 209ca5f80aeSKoen Kooi * Description: This function checks for expansion board by checking I2C 210ca5f80aeSKoen Kooi * bus 1 for the availability of an AT24C01B serial EEPROM. 211ca5f80aeSKoen Kooi * returns the device_vendor field from the EEPROM 212ca5f80aeSKoen Kooi */ 213ca5f80aeSKoen Kooi unsigned int get_expansion_id(void) 214ca5f80aeSKoen Kooi { 215ca5f80aeSKoen Kooi i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS); 216ca5f80aeSKoen Kooi 217ca5f80aeSKoen Kooi /* return BEAGLE_NO_EEPROM if eeprom doesn't respond */ 218ca5f80aeSKoen Kooi if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) { 219ca5f80aeSKoen Kooi i2c_set_bus_num(TWL4030_I2C_BUS); 220ca5f80aeSKoen Kooi return BEAGLE_NO_EEPROM; 221ca5f80aeSKoen Kooi } 222ca5f80aeSKoen Kooi 223ca5f80aeSKoen Kooi /* read configuration data */ 224ca5f80aeSKoen Kooi i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config, 225ca5f80aeSKoen Kooi sizeof(expansion_config)); 226ca5f80aeSKoen Kooi 227ca5f80aeSKoen Kooi i2c_set_bus_num(TWL4030_I2C_BUS); 228ca5f80aeSKoen Kooi 229ca5f80aeSKoen Kooi return expansion_config.device_vendor; 230ca5f80aeSKoen Kooi } 231ca5f80aeSKoen Kooi 232ca5f80aeSKoen Kooi /* 2333f16ab91SJason Kridner * Configure DSS to display background color on DVID 2343f16ab91SJason Kridner * Configure VENC to display color bar on S-Video 2353f16ab91SJason Kridner */ 2363f16ab91SJason Kridner void beagle_display_init(void) 2373f16ab91SJason Kridner { 2383f16ab91SJason Kridner omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); 2393f16ab91SJason Kridner switch (get_board_revision()) { 2403f16ab91SJason Kridner case REVISION_AXBX: 2413f16ab91SJason Kridner case REVISION_CX: 2423f16ab91SJason Kridner case REVISION_C4: 2433f16ab91SJason Kridner omap3_dss_panel_config(&dvid_cfg); 2443f16ab91SJason Kridner break; 2453f16ab91SJason Kridner case REVISION_XM_A: 2463f16ab91SJason Kridner case REVISION_XM_B: 2473f16ab91SJason Kridner case REVISION_XM_C: 2483f16ab91SJason Kridner default: 2493f16ab91SJason Kridner omap3_dss_panel_config(&dvid_cfg_xm); 2503f16ab91SJason Kridner break; 2513f16ab91SJason Kridner } 2523f16ab91SJason Kridner } 2533f16ab91SJason Kridner 2543f16ab91SJason Kridner /* 2554258aa62SPeter Meerwald * Enable DVI power 2564258aa62SPeter Meerwald */ 2573fbc6931SAnatolij Gustschin static void beagle_dvi_pup(void) 2583fbc6931SAnatolij Gustschin { 2594258aa62SPeter Meerwald uchar val; 2604258aa62SPeter Meerwald 2614258aa62SPeter Meerwald switch (get_board_revision()) { 2624258aa62SPeter Meerwald case REVISION_AXBX: 2634258aa62SPeter Meerwald case REVISION_CX: 2644258aa62SPeter Meerwald case REVISION_C4: 2654258aa62SPeter Meerwald case REVISION_XM_A: 2664258aa62SPeter Meerwald gpio_request(170, ""); 2674258aa62SPeter Meerwald gpio_direction_output(170, 0); 2684258aa62SPeter Meerwald gpio_set_value(170, 1); 2694258aa62SPeter Meerwald break; 2704258aa62SPeter Meerwald case REVISION_XM_B: 2714258aa62SPeter Meerwald case REVISION_XM_C: 2724258aa62SPeter Meerwald default: 2734258aa62SPeter Meerwald #define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3) 2744258aa62SPeter Meerwald #define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6) 2754258aa62SPeter Meerwald 2764258aa62SPeter Meerwald i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); 2774258aa62SPeter Meerwald val |= 4; 2784258aa62SPeter Meerwald i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1); 2794258aa62SPeter Meerwald 2804258aa62SPeter Meerwald i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); 2814258aa62SPeter Meerwald val |= 4; 2824258aa62SPeter Meerwald i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1); 2834258aa62SPeter Meerwald break; 2844258aa62SPeter Meerwald } 2854258aa62SPeter Meerwald } 2864258aa62SPeter Meerwald 2874258aa62SPeter Meerwald /* 2880a0e4badSJean-Christophe PLAGNIOL-VILLARD * Routine: misc_init_r 2890a0e4badSJean-Christophe PLAGNIOL-VILLARD * Description: Configure board specific parts 2900a0e4badSJean-Christophe PLAGNIOL-VILLARD */ 2910a0e4badSJean-Christophe PLAGNIOL-VILLARD int misc_init_r(void) 2920a0e4badSJean-Christophe PLAGNIOL-VILLARD { 2930a0e4badSJean-Christophe PLAGNIOL-VILLARD struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; 2940a0e4badSJean-Christophe PLAGNIOL-VILLARD struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; 295f14a522aSJason Kridner struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; 296d4e53f06SSteve Kipisz 297d4e53f06SSteve Kipisz /* Enable i2c2 pullup resisters */ 298d4e53f06SSteve Kipisz writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1); 2990a0e4badSJean-Christophe PLAGNIOL-VILLARD 30006b95bd5SSteve Sakoman switch (get_board_revision()) { 30106b95bd5SSteve Sakoman case REVISION_AXBX: 30206b95bd5SSteve Sakoman printf("Beagle Rev Ax/Bx\n"); 30306b95bd5SSteve Sakoman setenv("beaglerev", "AxBx"); 30406b95bd5SSteve Sakoman break; 30506b95bd5SSteve Sakoman case REVISION_CX: 30606b95bd5SSteve Sakoman printf("Beagle Rev C1/C2/C3\n"); 30706b95bd5SSteve Sakoman setenv("beaglerev", "Cx"); 30806b95bd5SSteve Sakoman MUX_BEAGLE_C(); 30906b95bd5SSteve Sakoman break; 31006b95bd5SSteve Sakoman case REVISION_C4: 31106b95bd5SSteve Sakoman printf("Beagle Rev C4\n"); 31208cbba2aSSteve Sakoman setenv("beaglerev", "C4"); 31306b95bd5SSteve Sakoman MUX_BEAGLE_C(); 31406b95bd5SSteve Sakoman /* Set VAUX2 to 1.8V for EHCI PHY */ 31506b95bd5SSteve Sakoman twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 31606b95bd5SSteve Sakoman TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 31706b95bd5SSteve Sakoman TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 31806b95bd5SSteve Sakoman TWL4030_PM_RECEIVER_DEV_GRP_P1); 31906b95bd5SSteve Sakoman break; 320f6e593bbSKoen Kooi case REVISION_XM_A: 32108cbba2aSSteve Sakoman printf("Beagle xM Rev A\n"); 32208cbba2aSSteve Sakoman setenv("beaglerev", "xMA"); 323f6e593bbSKoen Kooi MUX_BEAGLE_XM(); 324f6e593bbSKoen Kooi /* Set VAUX2 to 1.8V for EHCI PHY */ 325f6e593bbSKoen Kooi twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 326f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 327f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 328f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_DEV_GRP_P1); 329f6e593bbSKoen Kooi break; 330f6e593bbSKoen Kooi case REVISION_XM_B: 331f6e593bbSKoen Kooi printf("Beagle xM Rev B\n"); 332f6e593bbSKoen Kooi setenv("beaglerev", "xMB"); 33308cbba2aSSteve Sakoman MUX_BEAGLE_XM(); 33408cbba2aSSteve Sakoman /* Set VAUX2 to 1.8V for EHCI PHY */ 33508cbba2aSSteve Sakoman twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 33608cbba2aSSteve Sakoman TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 33708cbba2aSSteve Sakoman TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 33808cbba2aSSteve Sakoman TWL4030_PM_RECEIVER_DEV_GRP_P1); 33908cbba2aSSteve Sakoman break; 3401ffcb346SKoen Kooi case REVISION_XM_C: 3411ffcb346SKoen Kooi printf("Beagle xM Rev C\n"); 3421ffcb346SKoen Kooi setenv("beaglerev", "xMC"); 3431ffcb346SKoen Kooi MUX_BEAGLE_XM(); 3441ffcb346SKoen Kooi /* Set VAUX2 to 1.8V for EHCI PHY */ 3451ffcb346SKoen Kooi twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 3461ffcb346SKoen Kooi TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 3471ffcb346SKoen Kooi TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 3481ffcb346SKoen Kooi TWL4030_PM_RECEIVER_DEV_GRP_P1); 3491ffcb346SKoen Kooi break; 35006b95bd5SSteve Sakoman default: 35106b95bd5SSteve Sakoman printf("Beagle unknown 0x%02x\n", get_board_revision()); 352f6e593bbSKoen Kooi MUX_BEAGLE_XM(); 353f6e593bbSKoen Kooi /* Set VAUX2 to 1.8V for EHCI PHY */ 354f6e593bbSKoen Kooi twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, 355f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_VAUX2_VSEL_18, 356f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, 357f6e593bbSKoen Kooi TWL4030_PM_RECEIVER_DEV_GRP_P1); 35806b95bd5SSteve Sakoman } 35906b95bd5SSteve Sakoman 360ca5f80aeSKoen Kooi switch (get_expansion_id()) { 361ca5f80aeSKoen Kooi case TINCANTOOLS_ZIPPY: 362ca5f80aeSKoen Kooi printf("Recognized Tincantools Zippy board (rev %d %s)\n", 363ca5f80aeSKoen Kooi expansion_config.revision, 364ca5f80aeSKoen Kooi expansion_config.fab_revision); 365ca5f80aeSKoen Kooi MUX_TINCANTOOLS_ZIPPY(); 366ca5f80aeSKoen Kooi setenv("buddy", "zippy"); 367ca5f80aeSKoen Kooi break; 368ca5f80aeSKoen Kooi case TINCANTOOLS_ZIPPY2: 369ca5f80aeSKoen Kooi printf("Recognized Tincantools Zippy2 board (rev %d %s)\n", 370ca5f80aeSKoen Kooi expansion_config.revision, 371ca5f80aeSKoen Kooi expansion_config.fab_revision); 372ca5f80aeSKoen Kooi MUX_TINCANTOOLS_ZIPPY(); 373ca5f80aeSKoen Kooi setenv("buddy", "zippy2"); 374ca5f80aeSKoen Kooi break; 375ca5f80aeSKoen Kooi case TINCANTOOLS_TRAINER: 376ca5f80aeSKoen Kooi printf("Recognized Tincantools Trainer board (rev %d %s)\n", 377ca5f80aeSKoen Kooi expansion_config.revision, 378ca5f80aeSKoen Kooi expansion_config.fab_revision); 379ca5f80aeSKoen Kooi MUX_TINCANTOOLS_ZIPPY(); 380ca5f80aeSKoen Kooi MUX_TINCANTOOLS_TRAINER(); 381ca5f80aeSKoen Kooi setenv("buddy", "trainer"); 382ca5f80aeSKoen Kooi break; 383ca5f80aeSKoen Kooi case TINCANTOOLS_SHOWDOG: 384ca5f80aeSKoen Kooi printf("Recognized Tincantools Showdow board (rev %d %s)\n", 385ca5f80aeSKoen Kooi expansion_config.revision, 386ca5f80aeSKoen Kooi expansion_config.fab_revision); 387ca5f80aeSKoen Kooi /* Place holder for DSS2 definition for showdog lcd */ 388ca5f80aeSKoen Kooi setenv("defaultdisplay", "showdoglcd"); 389ca5f80aeSKoen Kooi setenv("buddy", "showdog"); 390ca5f80aeSKoen Kooi break; 391ca5f80aeSKoen Kooi case KBADC_BEAGLEFPGA: 392ca5f80aeSKoen Kooi printf("Recognized KBADC Beagle FPGA board\n"); 393ca5f80aeSKoen Kooi MUX_KBADC_BEAGLEFPGA(); 394ca5f80aeSKoen Kooi setenv("buddy", "beaglefpga"); 395ca5f80aeSKoen Kooi break; 396ee8485fdSKoen Kooi case LW_BEAGLETOUCH: 397ee8485fdSKoen Kooi printf("Recognized Liquidware BeagleTouch board\n"); 398ee8485fdSKoen Kooi setenv("buddy", "beagletouch"); 399ee8485fdSKoen Kooi break; 400ee8485fdSKoen Kooi case BRAINMUX_LCDOG: 401ee8485fdSKoen Kooi printf("Recognized Brainmux LCDog board\n"); 402ee8485fdSKoen Kooi setenv("buddy", "lcdog"); 403ee8485fdSKoen Kooi break; 404ee8485fdSKoen Kooi case BRAINMUX_LCDOGTOUCH: 405ee8485fdSKoen Kooi printf("Recognized Brainmux LCDog Touch board\n"); 406ee8485fdSKoen Kooi setenv("buddy", "lcdogtouch"); 407ee8485fdSKoen Kooi break; 408ee8485fdSKoen Kooi case BBTOYS_WIFI: 409ee8485fdSKoen Kooi printf("Recognized BeagleBoardToys WiFi board\n"); 410ee8485fdSKoen Kooi MUX_BBTOYS_WIFI() 411ee8485fdSKoen Kooi setenv("buddy", "bbtoys-wifi"); 412ee8485fdSKoen Kooi break;; 413ee8485fdSKoen Kooi case BBTOYS_VGA: 414ee8485fdSKoen Kooi printf("Recognized BeagleBoardToys VGA board\n"); 415ee8485fdSKoen Kooi break;; 416ee8485fdSKoen Kooi case BBTOYS_LCD: 417ee8485fdSKoen Kooi printf("Recognized BeagleBoardToys LCD board\n"); 418ee8485fdSKoen Kooi break;; 4196cce5504SPeter Meerwald case BCT_BRETTL3: 4206cce5504SPeter Meerwald printf("Recognized bct electronic GmbH brettl3 board\n"); 4216cce5504SPeter Meerwald break; 422ca5f80aeSKoen Kooi case BEAGLE_NO_EEPROM: 423ca5f80aeSKoen Kooi printf("No EEPROM on expansion board\n"); 424ca5f80aeSKoen Kooi setenv("buddy", "none"); 425ca5f80aeSKoen Kooi break; 426ca5f80aeSKoen Kooi default: 427ca5f80aeSKoen Kooi printf("Unrecognized expansion board: %x\n", 428ca5f80aeSKoen Kooi expansion_config.device_vendor); 429ca5f80aeSKoen Kooi setenv("buddy", "unknown"); 430ca5f80aeSKoen Kooi } 431ca5f80aeSKoen Kooi 432ca5f80aeSKoen Kooi if (expansion_config.content == 1) 433ca5f80aeSKoen Kooi setenv(expansion_config.env_var, expansion_config.env_setting); 434ca5f80aeSKoen Kooi 4350a0e4badSJean-Christophe PLAGNIOL-VILLARD twl4030_power_init(); 43638a77c3aSChristian Spielberger switch (get_board_revision()) { 43738a77c3aSChristian Spielberger case REVISION_XM_A: 43838a77c3aSChristian Spielberger case REVISION_XM_B: 43938a77c3aSChristian Spielberger twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); 44038a77c3aSChristian Spielberger break; 44138a77c3aSChristian Spielberger default: 442ead39d7aSGrazvydas Ignotas twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 44338a77c3aSChristian Spielberger break; 44438a77c3aSChristian Spielberger } 4450a0e4badSJean-Christophe PLAGNIOL-VILLARD 44652d82e40SBob Feretich /* Set GPIO states before they are made outputs */ 4470a0e4badSJean-Christophe PLAGNIOL-VILLARD writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, 4480a0e4badSJean-Christophe PLAGNIOL-VILLARD &gpio6_base->setdataout); 4490a0e4badSJean-Christophe PLAGNIOL-VILLARD writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | 4500a0e4badSJean-Christophe PLAGNIOL-VILLARD GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); 4510a0e4badSJean-Christophe PLAGNIOL-VILLARD 45252d82e40SBob Feretich /* Configure GPIOs to output */ 45352d82e40SBob Feretich writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); 45452d82e40SBob Feretich writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | 45552d82e40SBob Feretich GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); 45652d82e40SBob Feretich 4570a0e4badSJean-Christophe PLAGNIOL-VILLARD dieid_num_r(); 4584258aa62SPeter Meerwald 4594258aa62SPeter Meerwald beagle_dvi_pup(); 4603f16ab91SJason Kridner beagle_display_init(); 4613f16ab91SJason Kridner omap3_dss_enable(); 4620a0e4badSJean-Christophe PLAGNIOL-VILLARD 4630a0e4badSJean-Christophe PLAGNIOL-VILLARD return 0; 4640a0e4badSJean-Christophe PLAGNIOL-VILLARD } 4650a0e4badSJean-Christophe PLAGNIOL-VILLARD 4660a0e4badSJean-Christophe PLAGNIOL-VILLARD /* 4670a0e4badSJean-Christophe PLAGNIOL-VILLARD * Routine: set_muxconf_regs 4680a0e4badSJean-Christophe PLAGNIOL-VILLARD * Description: Setting up the configuration Mux registers specific to the 4690a0e4badSJean-Christophe PLAGNIOL-VILLARD * hardware. Many pins need to be moved from protect to primary 4700a0e4badSJean-Christophe PLAGNIOL-VILLARD * mode. 4710a0e4badSJean-Christophe PLAGNIOL-VILLARD */ 4720a0e4badSJean-Christophe PLAGNIOL-VILLARD void set_muxconf_regs(void) 4730a0e4badSJean-Christophe PLAGNIOL-VILLARD { 4740a0e4badSJean-Christophe PLAGNIOL-VILLARD MUX_BEAGLE(); 4750a0e4badSJean-Christophe PLAGNIOL-VILLARD } 4760cd31144SSteve Sakoman 47775c57a35STom Rini #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 4780cd31144SSteve Sakoman int board_mmc_init(bd_t *bis) 4790cd31144SSteve Sakoman { 480*bbbc1ae9SJonathan Solnit omap_mmc_init(0, 0, 0); 4810cd31144SSteve Sakoman return 0; 4820cd31144SSteve Sakoman } 4830cd31144SSteve Sakoman #endif 484d90859a6SAlexander Holler 485d90859a6SAlexander Holler #ifdef CONFIG_USB_EHCI 486d90859a6SAlexander Holler /* Call usb_stop() before starting the kernel */ 487d90859a6SAlexander Holler void show_boot_progress(int val) 488d90859a6SAlexander Holler { 489578ac1e9SSimon Glass if (val == BOOTSTAGE_ID_RUN_OS) 490d90859a6SAlexander Holler usb_stop(); 491d90859a6SAlexander Holler } 49243b62393SGovindraj.R 49343b62393SGovindraj.R static struct omap_usbhs_board_data usbhs_bdata = { 49443b62393SGovindraj.R .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, 49543b62393SGovindraj.R .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, 49643b62393SGovindraj.R .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED 49743b62393SGovindraj.R }; 49843b62393SGovindraj.R 49943b62393SGovindraj.R int ehci_hcd_init(void) 50043b62393SGovindraj.R { 50143b62393SGovindraj.R return omap_ehci_hcd_init(&usbhs_bdata); 50243b62393SGovindraj.R } 50343b62393SGovindraj.R 50443b62393SGovindraj.R int ehci_hcd_stop(void) 50543b62393SGovindraj.R { 50643b62393SGovindraj.R return omap_ehci_hcd_stop(); 50743b62393SGovindraj.R } 50843b62393SGovindraj.R 509d90859a6SAlexander Holler #endif /* CONFIG_USB_EHCI */ 510