xref: /rk3399_rockchip-uboot/board/ti/beagle/beagle.c (revision 7ac2fe2da21d292aeaf3af74e5c80de9ce9dab56)
10a0e4badSJean-Christophe PLAGNIOL-VILLARD /*
275c57a35STom Rini  * (C) Copyright 2004-2011
30a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Texas Instruments, <www.ti.com>
40a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
50a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Author :
60a0e4badSJean-Christophe PLAGNIOL-VILLARD  *	Sunil Kumar <sunilsaini05@gmail.com>
70a0e4badSJean-Christophe PLAGNIOL-VILLARD  *	Shashi Ranjan <shashiranjanmca05@gmail.com>
80a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
90a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Derived from Beagle Board and 3430 SDP code by
100a0e4badSJean-Christophe PLAGNIOL-VILLARD  *	Richard Woodruff <r-woodruff2@ti.com>
110a0e4badSJean-Christophe PLAGNIOL-VILLARD  *	Syed Mohammed Khasim <khasim@ti.com>
120a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
130a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
140a0e4badSJean-Christophe PLAGNIOL-VILLARD  * See file CREDITS for list of people who contributed to this
150a0e4badSJean-Christophe PLAGNIOL-VILLARD  * project.
160a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
170a0e4badSJean-Christophe PLAGNIOL-VILLARD  * This program is free software; you can redistribute it and/or
180a0e4badSJean-Christophe PLAGNIOL-VILLARD  * modify it under the terms of the GNU General Public License as
190a0e4badSJean-Christophe PLAGNIOL-VILLARD  * published by the Free Software Foundation; either version 2 of
200a0e4badSJean-Christophe PLAGNIOL-VILLARD  * the License, or (at your option) any later version.
210a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
220a0e4badSJean-Christophe PLAGNIOL-VILLARD  * This program is distributed in the hope that it will be useful,
230a0e4badSJean-Christophe PLAGNIOL-VILLARD  * but WITHOUT ANY WARRANTY; without even the implied warranty of
240a0e4badSJean-Christophe PLAGNIOL-VILLARD  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
250a0e4badSJean-Christophe PLAGNIOL-VILLARD  * GNU General Public License for more details.
260a0e4badSJean-Christophe PLAGNIOL-VILLARD  *
270a0e4badSJean-Christophe PLAGNIOL-VILLARD  * You should have received a copy of the GNU General Public License
280a0e4badSJean-Christophe PLAGNIOL-VILLARD  * along with this program; if not, write to the Free Software
290a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
300a0e4badSJean-Christophe PLAGNIOL-VILLARD  * MA 02111-1307 USA
310a0e4badSJean-Christophe PLAGNIOL-VILLARD  */
320a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
3370d8c944SJason Kridner #ifdef CONFIG_STATUS_LED
3470d8c944SJason Kridner #include <status_led.h>
3570d8c944SJason Kridner #endif
360a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <twl4030.h>
3775c57a35STom Rini #include <linux/mtd/nand.h>
380a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
390cd31144SSteve Sakoman #include <asm/arch/mmc_host_def.h>
400a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/mux.h>
4175c57a35STom Rini #include <asm/arch/mem.h>
420a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/sys_proto.h>
4384c3b631SSanjeev Premi #include <asm/gpio.h>
440a0e4badSJean-Christophe PLAGNIOL-VILLARD #include <asm/mach-types.h>
450a0e4badSJean-Christophe PLAGNIOL-VILLARD #include "beagle.h"
46f835ea71SJason Kridner #include <command.h>
470a0e4badSJean-Christophe PLAGNIOL-VILLARD 
4843b62393SGovindraj.R #ifdef CONFIG_USB_EHCI
4943b62393SGovindraj.R #include <usb.h>
5043b62393SGovindraj.R #include <asm/ehci-omap.h>
5143b62393SGovindraj.R #endif
5243b62393SGovindraj.R 
53ca5f80aeSKoen Kooi #define TWL4030_I2C_BUS			0
54ca5f80aeSKoen Kooi #define EXPANSION_EEPROM_I2C_BUS	1
55ca5f80aeSKoen Kooi #define EXPANSION_EEPROM_I2C_ADDRESS	0x50
56ca5f80aeSKoen Kooi 
57ca5f80aeSKoen Kooi #define TINCANTOOLS_ZIPPY		0x01000100
58ca5f80aeSKoen Kooi #define TINCANTOOLS_ZIPPY2		0x02000100
59ca5f80aeSKoen Kooi #define TINCANTOOLS_TRAINER		0x04000100
60ca5f80aeSKoen Kooi #define TINCANTOOLS_SHOWDOG		0x03000100
61ca5f80aeSKoen Kooi #define KBADC_BEAGLEFPGA		0x01000600
62ee8485fdSKoen Kooi #define LW_BEAGLETOUCH			0x01000700
63ee8485fdSKoen Kooi #define BRAINMUX_LCDOG			0x01000800
64ee8485fdSKoen Kooi #define BRAINMUX_LCDOGTOUCH		0x02000800
65ee8485fdSKoen Kooi #define BBTOYS_WIFI			0x01000B00
66ee8485fdSKoen Kooi #define BBTOYS_VGA			0x02000B00
67ee8485fdSKoen Kooi #define BBTOYS_LCD			0x03000B00
686cce5504SPeter Meerwald #define BCT_BRETTL3			0x01000F00
69ef88e609SPeter Meerwald #define BCT_BRETTL4			0x02000F00
70ca5f80aeSKoen Kooi #define BEAGLE_NO_EEPROM		0xffffffff
71ca5f80aeSKoen Kooi 
7229565326SJohn Rigby DECLARE_GLOBAL_DATA_PTR;
7329565326SJohn Rigby 
74ca5f80aeSKoen Kooi static struct {
75ca5f80aeSKoen Kooi 	unsigned int device_vendor;
76ca5f80aeSKoen Kooi 	unsigned char revision;
77ca5f80aeSKoen Kooi 	unsigned char content;
78ca5f80aeSKoen Kooi 	char fab_revision[8];
79ca5f80aeSKoen Kooi 	char env_var[16];
80ca5f80aeSKoen Kooi 	char env_setting[64];
81ca5f80aeSKoen Kooi } expansion_config;
82ca5f80aeSKoen Kooi 
830a0e4badSJean-Christophe PLAGNIOL-VILLARD /*
840a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Routine: board_init
850a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Description: Early hardware init.
860a0e4badSJean-Christophe PLAGNIOL-VILLARD  */
870a0e4badSJean-Christophe PLAGNIOL-VILLARD int board_init(void)
880a0e4badSJean-Christophe PLAGNIOL-VILLARD {
890a0e4badSJean-Christophe PLAGNIOL-VILLARD 	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
900a0e4badSJean-Christophe PLAGNIOL-VILLARD 	/* board id for Linux */
910a0e4badSJean-Christophe PLAGNIOL-VILLARD 	gd->bd->bi_arch_number = MACH_TYPE_OMAP3_BEAGLE;
920a0e4badSJean-Christophe PLAGNIOL-VILLARD 	/* boot param addr */
930a0e4badSJean-Christophe PLAGNIOL-VILLARD 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
940a0e4badSJean-Christophe PLAGNIOL-VILLARD 
9570d8c944SJason Kridner #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
9670d8c944SJason Kridner 	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
9770d8c944SJason Kridner #endif
9870d8c944SJason Kridner 
990a0e4badSJean-Christophe PLAGNIOL-VILLARD 	return 0;
1000a0e4badSJean-Christophe PLAGNIOL-VILLARD }
1010a0e4badSJean-Christophe PLAGNIOL-VILLARD 
1020a0e4badSJean-Christophe PLAGNIOL-VILLARD /*
10306b95bd5SSteve Sakoman  * Routine: get_board_revision
10406b95bd5SSteve Sakoman  * Description: Detect if we are running on a Beagle revision Ax/Bx,
10508cbba2aSSteve Sakoman  *		C1/2/3, C4 or xM. This can be done by reading
10606b95bd5SSteve Sakoman  *		the level of GPIO173, GPIO172 and GPIO171. This should
10706b95bd5SSteve Sakoman  *		result in
10806b95bd5SSteve Sakoman  *		GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx
10906b95bd5SSteve Sakoman  *		GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3
11006b95bd5SSteve Sakoman  *		GPIO173, GPIO172, GPIO171: 1 0 1 => C4
11108cbba2aSSteve Sakoman  *		GPIO173, GPIO172, GPIO171: 0 0 0 => xM
1120a0e4badSJean-Christophe PLAGNIOL-VILLARD  */
113fff1a572SPeter Meerwald static int get_board_revision(void)
1140a0e4badSJean-Christophe PLAGNIOL-VILLARD {
11506b95bd5SSteve Sakoman 	int revision;
1160a0e4badSJean-Christophe PLAGNIOL-VILLARD 
11784c3b631SSanjeev Premi 	if (!gpio_request(171, "") &&
11884c3b631SSanjeev Premi 	    !gpio_request(172, "") &&
11984c3b631SSanjeev Premi 	    !gpio_request(173, "")) {
1200a0e4badSJean-Christophe PLAGNIOL-VILLARD 
12184c3b631SSanjeev Premi 		gpio_direction_input(171);
12284c3b631SSanjeev Premi 		gpio_direction_input(172);
12384c3b631SSanjeev Premi 		gpio_direction_input(173);
1240a0e4badSJean-Christophe PLAGNIOL-VILLARD 
12584c3b631SSanjeev Premi 		revision = gpio_get_value(173) << 2 |
12684c3b631SSanjeev Premi 			   gpio_get_value(172) << 1 |
12784c3b631SSanjeev Premi 			   gpio_get_value(171);
12806b95bd5SSteve Sakoman 	} else {
12906b95bd5SSteve Sakoman 		printf("Error: unable to acquire board revision GPIOs\n");
13006b95bd5SSteve Sakoman 		revision = -1;
1310a0e4badSJean-Christophe PLAGNIOL-VILLARD 	}
1320a0e4badSJean-Christophe PLAGNIOL-VILLARD 
13306b95bd5SSteve Sakoman 	return revision;
1340a0e4badSJean-Christophe PLAGNIOL-VILLARD }
1350a0e4badSJean-Christophe PLAGNIOL-VILLARD 
13675c57a35STom Rini #ifdef CONFIG_SPL_BUILD
13775c57a35STom Rini /*
13875c57a35STom Rini  * Routine: get_board_mem_timings
13975c57a35STom Rini  * Description: If we use SPL then there is no x-loader nor config header
14075c57a35STom Rini  * so we have to setup the DDR timings ourself on both banks.
14175c57a35STom Rini  */
14275c57a35STom Rini void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
14375c57a35STom Rini 		u32 *mr)
14475c57a35STom Rini {
14575c57a35STom Rini 	int pop_mfr, pop_id;
14675c57a35STom Rini 
14775c57a35STom Rini 	/*
14875c57a35STom Rini 	 * We need to identify what PoP memory is on the board so that
14975c57a35STom Rini 	 * we know what timings to use.  If we can't identify it then
15075c57a35STom Rini 	 * we know it's an xM.  To map the ID values please see nand_ids.c
15175c57a35STom Rini 	 */
15275c57a35STom Rini 	identify_nand_chip(&pop_mfr, &pop_id);
15375c57a35STom Rini 
15475c57a35STom Rini 	*mr = MICRON_V_MR_165;
15575c57a35STom Rini 	switch (get_board_revision()) {
15675c57a35STom Rini 	case REVISION_C4:
15775c57a35STom Rini 		if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
15875c57a35STom Rini 			/* 512MB DDR */
15975c57a35STom Rini 			*mcfg = NUMONYX_V_MCFG_165(512 << 20);
16075c57a35STom Rini 			*ctrla = NUMONYX_V_ACTIMA_165;
16175c57a35STom Rini 			*ctrlb = NUMONYX_V_ACTIMB_165;
16275c57a35STom Rini 			*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
16375c57a35STom Rini 			break;
164223b8aa4Srobertcnelson@gmail.com 		} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
165223b8aa4Srobertcnelson@gmail.com 			/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
166223b8aa4Srobertcnelson@gmail.com 			*mcfg = MICRON_V_MCFG_165(128 << 20);
167223b8aa4Srobertcnelson@gmail.com 			*ctrla = MICRON_V_ACTIMA_165;
168223b8aa4Srobertcnelson@gmail.com 			*ctrlb = MICRON_V_ACTIMB_165;
169223b8aa4Srobertcnelson@gmail.com 			*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
170223b8aa4Srobertcnelson@gmail.com 			break;
17175c57a35STom Rini 		} else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
17275c57a35STom Rini 			/* Beagleboard Rev C5, 256MB DDR */
17375c57a35STom Rini 			*mcfg = MICRON_V_MCFG_200(256 << 20);
17475c57a35STom Rini 			*ctrla = MICRON_V_ACTIMA_200;
17575c57a35STom Rini 			*ctrlb = MICRON_V_ACTIMB_200;
17675c57a35STom Rini 			*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
17775c57a35STom Rini 			break;
17875c57a35STom Rini 		}
17975c57a35STom Rini 	case REVISION_XM_A:
18075c57a35STom Rini 	case REVISION_XM_B:
18175c57a35STom Rini 	case REVISION_XM_C:
18275c57a35STom Rini 		if (pop_mfr == 0) {
18375c57a35STom Rini 			/* 256MB DDR */
18475c57a35STom Rini 			*mcfg = MICRON_V_MCFG_200(256 << 20);
18575c57a35STom Rini 			*ctrla = MICRON_V_ACTIMA_200;
18675c57a35STom Rini 			*ctrlb = MICRON_V_ACTIMB_200;
18775c57a35STom Rini 			*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
18875c57a35STom Rini 		} else {
18975c57a35STom Rini 			/* 512MB DDR */
19075c57a35STom Rini 			*mcfg = NUMONYX_V_MCFG_165(512 << 20);
19175c57a35STom Rini 			*ctrla = NUMONYX_V_ACTIMA_165;
19275c57a35STom Rini 			*ctrlb = NUMONYX_V_ACTIMB_165;
19375c57a35STom Rini 			*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
19475c57a35STom Rini 		}
19575c57a35STom Rini 		break;
19675c57a35STom Rini 	default:
19775c57a35STom Rini 		/* Assume 128MB and Micron/165MHz timings to be safe */
19875c57a35STom Rini 		*mcfg = MICRON_V_MCFG_165(128 << 20);
19975c57a35STom Rini 		*ctrla = MICRON_V_ACTIMA_165;
20075c57a35STom Rini 		*ctrlb = MICRON_V_ACTIMB_165;
20175c57a35STom Rini 		*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
20275c57a35STom Rini 	}
20375c57a35STom Rini }
20475c57a35STom Rini #endif
20575c57a35STom Rini 
2060a0e4badSJean-Christophe PLAGNIOL-VILLARD /*
207ca5f80aeSKoen Kooi  * Routine: get_expansion_id
208ca5f80aeSKoen Kooi  * Description: This function checks for expansion board by checking I2C
209ca5f80aeSKoen Kooi  *		bus 1 for the availability of an AT24C01B serial EEPROM.
210ca5f80aeSKoen Kooi  *		returns the device_vendor field from the EEPROM
211ca5f80aeSKoen Kooi  */
212fff1a572SPeter Meerwald static unsigned int get_expansion_id(void)
213ca5f80aeSKoen Kooi {
214ca5f80aeSKoen Kooi 	i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
215ca5f80aeSKoen Kooi 
216ca5f80aeSKoen Kooi 	/* return BEAGLE_NO_EEPROM if eeprom doesn't respond */
217ca5f80aeSKoen Kooi 	if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
218ca5f80aeSKoen Kooi 		i2c_set_bus_num(TWL4030_I2C_BUS);
219ca5f80aeSKoen Kooi 		return BEAGLE_NO_EEPROM;
220ca5f80aeSKoen Kooi 	}
221ca5f80aeSKoen Kooi 
222ca5f80aeSKoen Kooi 	/* read configuration data */
223ca5f80aeSKoen Kooi 	i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
224ca5f80aeSKoen Kooi 		 sizeof(expansion_config));
225ca5f80aeSKoen Kooi 
226ca5f80aeSKoen Kooi 	i2c_set_bus_num(TWL4030_I2C_BUS);
227ca5f80aeSKoen Kooi 
228ca5f80aeSKoen Kooi 	return expansion_config.device_vendor;
229ca5f80aeSKoen Kooi }
230ca5f80aeSKoen Kooi 
2312c30c184SPeter Meerwald #ifdef CONFIG_VIDEO_OMAP3
232ca5f80aeSKoen Kooi /*
2333f16ab91SJason Kridner  * Configure DSS to display background color on DVID
2343f16ab91SJason Kridner  * Configure VENC to display color bar on S-Video
2353f16ab91SJason Kridner  */
236fff1a572SPeter Meerwald static void beagle_display_init(void)
2373f16ab91SJason Kridner {
2383f16ab91SJason Kridner 	omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH);
2393f16ab91SJason Kridner 	switch (get_board_revision()) {
2403f16ab91SJason Kridner 	case REVISION_AXBX:
2413f16ab91SJason Kridner 	case REVISION_CX:
2423f16ab91SJason Kridner 	case REVISION_C4:
2433f16ab91SJason Kridner 		omap3_dss_panel_config(&dvid_cfg);
2443f16ab91SJason Kridner 		break;
2453f16ab91SJason Kridner 	case REVISION_XM_A:
2463f16ab91SJason Kridner 	case REVISION_XM_B:
2473f16ab91SJason Kridner 	case REVISION_XM_C:
2483f16ab91SJason Kridner 	default:
2493f16ab91SJason Kridner 		omap3_dss_panel_config(&dvid_cfg_xm);
2503f16ab91SJason Kridner 		break;
2513f16ab91SJason Kridner 	}
2523f16ab91SJason Kridner }
2533f16ab91SJason Kridner 
2543f16ab91SJason Kridner /*
2554258aa62SPeter Meerwald  * Enable DVI power
2564258aa62SPeter Meerwald  */
2573fbc6931SAnatolij Gustschin static void beagle_dvi_pup(void)
2583fbc6931SAnatolij Gustschin {
2594258aa62SPeter Meerwald 	uchar val;
2604258aa62SPeter Meerwald 
2614258aa62SPeter Meerwald 	switch (get_board_revision()) {
2624258aa62SPeter Meerwald 	case REVISION_AXBX:
2634258aa62SPeter Meerwald 	case REVISION_CX:
2644258aa62SPeter Meerwald 	case REVISION_C4:
2654258aa62SPeter Meerwald 	case REVISION_XM_A:
2664258aa62SPeter Meerwald 		gpio_request(170, "");
2674258aa62SPeter Meerwald 		gpio_direction_output(170, 0);
2684258aa62SPeter Meerwald 		gpio_set_value(170, 1);
2694258aa62SPeter Meerwald 		break;
2704258aa62SPeter Meerwald 	case REVISION_XM_B:
2714258aa62SPeter Meerwald 	case REVISION_XM_C:
2724258aa62SPeter Meerwald 	default:
2734258aa62SPeter Meerwald 		#define GPIODATADIR1 (TWL4030_BASEADD_GPIO+3)
2744258aa62SPeter Meerwald 		#define GPIODATAOUT1 (TWL4030_BASEADD_GPIO+6)
2754258aa62SPeter Meerwald 
2764258aa62SPeter Meerwald 		i2c_read(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
2774258aa62SPeter Meerwald 		val |= 4;
2784258aa62SPeter Meerwald 		i2c_write(TWL4030_CHIP_GPIO, GPIODATADIR1, 1, &val, 1);
2794258aa62SPeter Meerwald 
2804258aa62SPeter Meerwald 		i2c_read(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
2814258aa62SPeter Meerwald 		val |= 4;
2824258aa62SPeter Meerwald 		i2c_write(TWL4030_CHIP_GPIO, GPIODATAOUT1, 1, &val, 1);
2834258aa62SPeter Meerwald 		break;
2844258aa62SPeter Meerwald 	}
2854258aa62SPeter Meerwald }
2862c30c184SPeter Meerwald #endif
2874258aa62SPeter Meerwald 
2884258aa62SPeter Meerwald /*
2890a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Routine: misc_init_r
2900a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Description: Configure board specific parts
2910a0e4badSJean-Christophe PLAGNIOL-VILLARD  */
2920a0e4badSJean-Christophe PLAGNIOL-VILLARD int misc_init_r(void)
2930a0e4badSJean-Christophe PLAGNIOL-VILLARD {
2940a0e4badSJean-Christophe PLAGNIOL-VILLARD 	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
2950a0e4badSJean-Christophe PLAGNIOL-VILLARD 	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
296f14a522aSJason Kridner 	struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE;
297d4e53f06SSteve Kipisz 
298d4e53f06SSteve Kipisz 	/* Enable i2c2 pullup resisters */
299d4e53f06SSteve Kipisz 	writel(~(PRG_I2C2_PULLUPRESX), &prog_io_base->io1);
3000a0e4badSJean-Christophe PLAGNIOL-VILLARD 
30106b95bd5SSteve Sakoman 	switch (get_board_revision()) {
30206b95bd5SSteve Sakoman 	case REVISION_AXBX:
30306b95bd5SSteve Sakoman 		printf("Beagle Rev Ax/Bx\n");
30406b95bd5SSteve Sakoman 		setenv("beaglerev", "AxBx");
30506b95bd5SSteve Sakoman 		break;
30606b95bd5SSteve Sakoman 	case REVISION_CX:
30706b95bd5SSteve Sakoman 		printf("Beagle Rev C1/C2/C3\n");
30806b95bd5SSteve Sakoman 		setenv("beaglerev", "Cx");
30906b95bd5SSteve Sakoman 		MUX_BEAGLE_C();
31006b95bd5SSteve Sakoman 		break;
31106b95bd5SSteve Sakoman 	case REVISION_C4:
31206b95bd5SSteve Sakoman 		printf("Beagle Rev C4\n");
31308cbba2aSSteve Sakoman 		setenv("beaglerev", "C4");
31406b95bd5SSteve Sakoman 		MUX_BEAGLE_C();
31506b95bd5SSteve Sakoman 		/* Set VAUX2 to 1.8V for EHCI PHY */
31606b95bd5SSteve Sakoman 		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
31706b95bd5SSteve Sakoman 					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
31806b95bd5SSteve Sakoman 					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
31906b95bd5SSteve Sakoman 					TWL4030_PM_RECEIVER_DEV_GRP_P1);
32006b95bd5SSteve Sakoman 		break;
321f6e593bbSKoen Kooi 	case REVISION_XM_A:
32208cbba2aSSteve Sakoman 		printf("Beagle xM Rev A\n");
32308cbba2aSSteve Sakoman 		setenv("beaglerev", "xMA");
324f6e593bbSKoen Kooi 		MUX_BEAGLE_XM();
325f6e593bbSKoen Kooi 		/* Set VAUX2 to 1.8V for EHCI PHY */
326f6e593bbSKoen Kooi 		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
327f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
328f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
329f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_DEV_GRP_P1);
330f6e593bbSKoen Kooi 		break;
331f6e593bbSKoen Kooi 	case REVISION_XM_B:
332f6e593bbSKoen Kooi 		printf("Beagle xM Rev B\n");
333f6e593bbSKoen Kooi 		setenv("beaglerev", "xMB");
33408cbba2aSSteve Sakoman 		MUX_BEAGLE_XM();
33508cbba2aSSteve Sakoman 		/* Set VAUX2 to 1.8V for EHCI PHY */
33608cbba2aSSteve Sakoman 		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
33708cbba2aSSteve Sakoman 					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
33808cbba2aSSteve Sakoman 					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
33908cbba2aSSteve Sakoman 					TWL4030_PM_RECEIVER_DEV_GRP_P1);
34008cbba2aSSteve Sakoman 		break;
3411ffcb346SKoen Kooi 	case REVISION_XM_C:
3421ffcb346SKoen Kooi 		printf("Beagle xM Rev C\n");
3431ffcb346SKoen Kooi 		setenv("beaglerev", "xMC");
3441ffcb346SKoen Kooi 		MUX_BEAGLE_XM();
3451ffcb346SKoen Kooi 		/* Set VAUX2 to 1.8V for EHCI PHY */
3461ffcb346SKoen Kooi 		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
3471ffcb346SKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
3481ffcb346SKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
3491ffcb346SKoen Kooi 					TWL4030_PM_RECEIVER_DEV_GRP_P1);
3501ffcb346SKoen Kooi 		break;
35106b95bd5SSteve Sakoman 	default:
35206b95bd5SSteve Sakoman 		printf("Beagle unknown 0x%02x\n", get_board_revision());
353f6e593bbSKoen Kooi 		MUX_BEAGLE_XM();
354f6e593bbSKoen Kooi 		/* Set VAUX2 to 1.8V for EHCI PHY */
355f6e593bbSKoen Kooi 		twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
356f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_VSEL_18,
357f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
358f6e593bbSKoen Kooi 					TWL4030_PM_RECEIVER_DEV_GRP_P1);
35906b95bd5SSteve Sakoman 	}
36006b95bd5SSteve Sakoman 
361ca5f80aeSKoen Kooi 	switch (get_expansion_id()) {
362ca5f80aeSKoen Kooi 	case TINCANTOOLS_ZIPPY:
363ca5f80aeSKoen Kooi 		printf("Recognized Tincantools Zippy board (rev %d %s)\n",
364ca5f80aeSKoen Kooi 			expansion_config.revision,
365ca5f80aeSKoen Kooi 			expansion_config.fab_revision);
366ca5f80aeSKoen Kooi 		MUX_TINCANTOOLS_ZIPPY();
367ca5f80aeSKoen Kooi 		setenv("buddy", "zippy");
368ca5f80aeSKoen Kooi 		break;
369ca5f80aeSKoen Kooi 	case TINCANTOOLS_ZIPPY2:
370ca5f80aeSKoen Kooi 		printf("Recognized Tincantools Zippy2 board (rev %d %s)\n",
371ca5f80aeSKoen Kooi 			expansion_config.revision,
372ca5f80aeSKoen Kooi 			expansion_config.fab_revision);
373ca5f80aeSKoen Kooi 		MUX_TINCANTOOLS_ZIPPY();
374ca5f80aeSKoen Kooi 		setenv("buddy", "zippy2");
375ca5f80aeSKoen Kooi 		break;
376ca5f80aeSKoen Kooi 	case TINCANTOOLS_TRAINER:
377ca5f80aeSKoen Kooi 		printf("Recognized Tincantools Trainer board (rev %d %s)\n",
378ca5f80aeSKoen Kooi 			expansion_config.revision,
379ca5f80aeSKoen Kooi 			expansion_config.fab_revision);
380ca5f80aeSKoen Kooi 		MUX_TINCANTOOLS_ZIPPY();
381ca5f80aeSKoen Kooi 		MUX_TINCANTOOLS_TRAINER();
382ca5f80aeSKoen Kooi 		setenv("buddy", "trainer");
383ca5f80aeSKoen Kooi 		break;
384ca5f80aeSKoen Kooi 	case TINCANTOOLS_SHOWDOG:
385ca5f80aeSKoen Kooi 		printf("Recognized Tincantools Showdow board (rev %d %s)\n",
386ca5f80aeSKoen Kooi 			expansion_config.revision,
387ca5f80aeSKoen Kooi 			expansion_config.fab_revision);
388ca5f80aeSKoen Kooi 		/* Place holder for DSS2 definition for showdog lcd */
389ca5f80aeSKoen Kooi 		setenv("defaultdisplay", "showdoglcd");
390ca5f80aeSKoen Kooi 		setenv("buddy", "showdog");
391ca5f80aeSKoen Kooi 		break;
392ca5f80aeSKoen Kooi 	case KBADC_BEAGLEFPGA:
393ca5f80aeSKoen Kooi 		printf("Recognized KBADC Beagle FPGA board\n");
394ca5f80aeSKoen Kooi 		MUX_KBADC_BEAGLEFPGA();
395ca5f80aeSKoen Kooi 		setenv("buddy", "beaglefpga");
396ca5f80aeSKoen Kooi 		break;
397ee8485fdSKoen Kooi 	case LW_BEAGLETOUCH:
398ee8485fdSKoen Kooi 		printf("Recognized Liquidware BeagleTouch board\n");
399ee8485fdSKoen Kooi 		setenv("buddy", "beagletouch");
400ee8485fdSKoen Kooi 		break;
401ee8485fdSKoen Kooi 	case BRAINMUX_LCDOG:
402ee8485fdSKoen Kooi 		printf("Recognized Brainmux LCDog board\n");
403ee8485fdSKoen Kooi 		setenv("buddy", "lcdog");
404ee8485fdSKoen Kooi 		break;
405ee8485fdSKoen Kooi 	case BRAINMUX_LCDOGTOUCH:
406ee8485fdSKoen Kooi 		printf("Recognized Brainmux LCDog Touch board\n");
407ee8485fdSKoen Kooi 		setenv("buddy", "lcdogtouch");
408ee8485fdSKoen Kooi 		break;
409ee8485fdSKoen Kooi 	case BBTOYS_WIFI:
410ee8485fdSKoen Kooi 		printf("Recognized BeagleBoardToys WiFi board\n");
411ee8485fdSKoen Kooi 		MUX_BBTOYS_WIFI()
412ee8485fdSKoen Kooi 		setenv("buddy", "bbtoys-wifi");
413ee8485fdSKoen Kooi 		break;;
414ee8485fdSKoen Kooi 	case BBTOYS_VGA:
415ee8485fdSKoen Kooi 		printf("Recognized BeagleBoardToys VGA board\n");
416ee8485fdSKoen Kooi 		break;;
417ee8485fdSKoen Kooi 	case BBTOYS_LCD:
418ee8485fdSKoen Kooi 		printf("Recognized BeagleBoardToys LCD board\n");
419ee8485fdSKoen Kooi 		break;;
4206cce5504SPeter Meerwald 	case BCT_BRETTL3:
4216cce5504SPeter Meerwald 		printf("Recognized bct electronic GmbH brettl3 board\n");
4226cce5504SPeter Meerwald 		break;
423ef88e609SPeter Meerwald 	case BCT_BRETTL4:
424ef88e609SPeter Meerwald 		printf("Recognized bct electronic GmbH brettl4 board\n");
425ef88e609SPeter Meerwald 		break;
426ca5f80aeSKoen Kooi 	case BEAGLE_NO_EEPROM:
427ca5f80aeSKoen Kooi 		printf("No EEPROM on expansion board\n");
428ca5f80aeSKoen Kooi 		setenv("buddy", "none");
429ca5f80aeSKoen Kooi 		break;
430ca5f80aeSKoen Kooi 	default:
431ca5f80aeSKoen Kooi 		printf("Unrecognized expansion board: %x\n",
432ca5f80aeSKoen Kooi 			expansion_config.device_vendor);
433ca5f80aeSKoen Kooi 		setenv("buddy", "unknown");
434ca5f80aeSKoen Kooi 	}
435ca5f80aeSKoen Kooi 
436ca5f80aeSKoen Kooi 	if (expansion_config.content == 1)
437ca5f80aeSKoen Kooi 		setenv(expansion_config.env_var, expansion_config.env_setting);
438ca5f80aeSKoen Kooi 
4390a0e4badSJean-Christophe PLAGNIOL-VILLARD 	twl4030_power_init();
44038a77c3aSChristian Spielberger 	switch (get_board_revision()) {
44138a77c3aSChristian Spielberger 	case REVISION_XM_A:
44238a77c3aSChristian Spielberger 	case REVISION_XM_B:
44338a77c3aSChristian Spielberger 		twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
44438a77c3aSChristian Spielberger 		break;
44538a77c3aSChristian Spielberger 	default:
446ead39d7aSGrazvydas Ignotas 		twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
44738a77c3aSChristian Spielberger 		break;
44838a77c3aSChristian Spielberger 	}
4490a0e4badSJean-Christophe PLAGNIOL-VILLARD 
45052d82e40SBob Feretich 	/* Set GPIO states before they are made outputs */
4510a0e4badSJean-Christophe PLAGNIOL-VILLARD 	writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,
4520a0e4badSJean-Christophe PLAGNIOL-VILLARD 		&gpio6_base->setdataout);
4530a0e4badSJean-Christophe PLAGNIOL-VILLARD 	writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
4540a0e4badSJean-Christophe PLAGNIOL-VILLARD 		GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);
4550a0e4badSJean-Christophe PLAGNIOL-VILLARD 
45652d82e40SBob Feretich 	/* Configure GPIOs to output */
45752d82e40SBob Feretich 	writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);
45852d82e40SBob Feretich 	writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |
45952d82e40SBob Feretich 		GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);
46052d82e40SBob Feretich 
4610a0e4badSJean-Christophe PLAGNIOL-VILLARD 	dieid_num_r();
4624258aa62SPeter Meerwald 
4632c30c184SPeter Meerwald #ifdef CONFIG_VIDEO_OMAP3
4644258aa62SPeter Meerwald 	beagle_dvi_pup();
4653f16ab91SJason Kridner 	beagle_display_init();
4663f16ab91SJason Kridner 	omap3_dss_enable();
4672c30c184SPeter Meerwald #endif
4680a0e4badSJean-Christophe PLAGNIOL-VILLARD 
4690a0e4badSJean-Christophe PLAGNIOL-VILLARD 	return 0;
4700a0e4badSJean-Christophe PLAGNIOL-VILLARD }
4710a0e4badSJean-Christophe PLAGNIOL-VILLARD 
4720a0e4badSJean-Christophe PLAGNIOL-VILLARD /*
4730a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Routine: set_muxconf_regs
4740a0e4badSJean-Christophe PLAGNIOL-VILLARD  * Description: Setting up the configuration Mux registers specific to the
4750a0e4badSJean-Christophe PLAGNIOL-VILLARD  *		hardware. Many pins need to be moved from protect to primary
4760a0e4badSJean-Christophe PLAGNIOL-VILLARD  *		mode.
4770a0e4badSJean-Christophe PLAGNIOL-VILLARD  */
4780a0e4badSJean-Christophe PLAGNIOL-VILLARD void set_muxconf_regs(void)
4790a0e4badSJean-Christophe PLAGNIOL-VILLARD {
4800a0e4badSJean-Christophe PLAGNIOL-VILLARD 	MUX_BEAGLE();
4810a0e4badSJean-Christophe PLAGNIOL-VILLARD }
4820cd31144SSteve Sakoman 
48375c57a35STom Rini #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
4840cd31144SSteve Sakoman int board_mmc_init(bd_t *bis)
4850cd31144SSteve Sakoman {
486bbbc1ae9SJonathan Solnit 	omap_mmc_init(0, 0, 0);
4870cd31144SSteve Sakoman 	return 0;
4880cd31144SSteve Sakoman }
4890cd31144SSteve Sakoman #endif
490d90859a6SAlexander Holler 
491*7ac2fe2dSIlya Yanok #if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
492d90859a6SAlexander Holler /* Call usb_stop() before starting the kernel */
493d90859a6SAlexander Holler void show_boot_progress(int val)
494d90859a6SAlexander Holler {
495578ac1e9SSimon Glass 	if (val == BOOTSTAGE_ID_RUN_OS)
496d90859a6SAlexander Holler 		usb_stop();
497d90859a6SAlexander Holler }
49843b62393SGovindraj.R 
49943b62393SGovindraj.R static struct omap_usbhs_board_data usbhs_bdata = {
50043b62393SGovindraj.R 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
50143b62393SGovindraj.R 	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
50243b62393SGovindraj.R 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
50343b62393SGovindraj.R };
50443b62393SGovindraj.R 
50543b62393SGovindraj.R int ehci_hcd_init(void)
50643b62393SGovindraj.R {
50743b62393SGovindraj.R 	return omap_ehci_hcd_init(&usbhs_bdata);
50843b62393SGovindraj.R }
50943b62393SGovindraj.R 
51043b62393SGovindraj.R int ehci_hcd_stop(void)
51143b62393SGovindraj.R {
51243b62393SGovindraj.R 	return omap_ehci_hcd_stop();
51343b62393SGovindraj.R }
51443b62393SGovindraj.R 
515d90859a6SAlexander Holler #endif /* CONFIG_USB_EHCI */
516