1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <spl.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/mux.h> 18 #include <asm/arch/ddr_defs.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/emif.h> 21 #include "board.h" 22 #include <power/pmic.h> 23 #include <power/tps65218.h> 24 #include <miiphy.h> 25 #include <cpsw.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 30 31 /* 32 * Read header information from EEPROM into global structure. 33 */ 34 static int read_eeprom(struct am43xx_board_id *header) 35 { 36 /* Check if baseboard eeprom is available */ 37 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 38 printf("Could not probe the EEPROM at 0x%x\n", 39 CONFIG_SYS_I2C_EEPROM_ADDR); 40 return -ENODEV; 41 } 42 43 /* read the eeprom using i2c */ 44 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 45 sizeof(struct am43xx_board_id))) { 46 printf("Could not read the EEPROM\n"); 47 return -EIO; 48 } 49 50 if (header->magic != 0xEE3355AA) { 51 /* 52 * read the eeprom using i2c again, 53 * but use only a 1 byte address 54 */ 55 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 56 sizeof(struct am43xx_board_id))) { 57 printf("Could not read the EEPROM at 0x%x\n", 58 CONFIG_SYS_I2C_EEPROM_ADDR); 59 return -EIO; 60 } 61 62 if (header->magic != 0xEE3355AA) { 63 printf("Incorrect magic number (0x%x) in EEPROM\n", 64 header->magic); 65 return -EINVAL; 66 } 67 } 68 69 strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name)); 70 am43xx_board_name[sizeof(header->name)] = 0; 71 72 strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version)); 73 am43xx_board_rev[sizeof(header->version)] = 0; 74 75 return 0; 76 } 77 78 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 79 80 #define NUM_OPPS 6 81 82 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 83 { /* 19.2 MHz */ 84 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 85 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 86 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 87 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 88 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 89 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 90 }, 91 { /* 24 MHz */ 92 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 93 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 94 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 95 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 96 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 97 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 98 }, 99 { /* 25 MHz */ 100 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 101 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 102 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 103 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 104 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 105 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 106 }, 107 { /* 26 MHz */ 108 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 109 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 110 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 111 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 112 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 113 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 114 }, 115 }; 116 117 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 118 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 119 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 120 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 121 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 122 }; 123 124 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 125 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 126 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 127 {32, 0, 8, -1, -1, -1, -1}, /* 25 MHz */ 128 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 129 }; 130 131 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 132 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 133 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 134 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 135 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 136 }; 137 138 const struct dpll_params gp_evm_dpll_ddr = { 139 50, 2, 1, -1, 2, -1, -1}; 140 141 const struct ctrl_ioregs ioregs_lpddr2 = { 142 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 143 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 144 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 145 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 148 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 149 .emif_sdram_config_ext = 0x1, 150 }; 151 152 const struct emif_regs emif_regs_lpddr2 = { 153 .sdram_config = 0x808012BA, 154 .ref_ctrl = 0x0000040D, 155 .sdram_tim1 = 0xEA86B411, 156 .sdram_tim2 = 0x103A094A, 157 .sdram_tim3 = 0x0F6BA37F, 158 .read_idle_ctrl = 0x00050000, 159 .zq_config = 0x50074BE4, 160 .temp_alert_config = 0x0, 161 .emif_rd_wr_lvl_rmp_win = 0x0, 162 .emif_rd_wr_lvl_rmp_ctl = 0x0, 163 .emif_rd_wr_lvl_ctl = 0x0, 164 .emif_ddr_phy_ctlr_1 = 0x0E284006, 165 .emif_rd_wr_exec_thresh = 0x80000405, 166 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 167 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 169 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 170 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 171 .emif_prio_class_serv_map = 0x80000001, 172 .emif_connect_id_serv_1_map = 0x80000094, 173 .emif_connect_id_serv_2_map = 0x00000000, 174 .emif_cos_config = 0x000FFFFF 175 }; 176 177 const struct ctrl_ioregs ioregs_ddr3 = { 178 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 179 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 180 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 181 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 183 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 184 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 185 .emif_sdram_config_ext = 0xc163, 186 }; 187 188 const struct emif_regs ddr3_emif_regs_400Mhz = { 189 .sdram_config = 0x638413B2, 190 .ref_ctrl = 0x00000C30, 191 .sdram_tim1 = 0xEAAAD4DB, 192 .sdram_tim2 = 0x266B7FDA, 193 .sdram_tim3 = 0x107F8678, 194 .read_idle_ctrl = 0x00050000, 195 .zq_config = 0x50074BE4, 196 .temp_alert_config = 0x0, 197 .emif_ddr_phy_ctlr_1 = 0x0E004008, 198 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 199 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 201 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 202 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 203 .emif_rd_wr_lvl_rmp_win = 0x0, 204 .emif_rd_wr_lvl_rmp_ctl = 0x0, 205 .emif_rd_wr_lvl_ctl = 0x0, 206 .emif_rd_wr_exec_thresh = 0x80000405, 207 .emif_prio_class_serv_map = 0x80000001, 208 .emif_connect_id_serv_1_map = 0x80000094, 209 .emif_connect_id_serv_2_map = 0x00000000, 210 .emif_cos_config = 0x000FFFFF 211 }; 212 213 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 214 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 215 .sdram_config = 0x638413B2, 216 .ref_ctrl = 0x00000C30, 217 .sdram_tim1 = 0xEAAAD4DB, 218 .sdram_tim2 = 0x266B7FDA, 219 .sdram_tim3 = 0x107F8678, 220 .read_idle_ctrl = 0x00050000, 221 .zq_config = 0x50074BE4, 222 .temp_alert_config = 0x0, 223 .emif_ddr_phy_ctlr_1 = 0x0E004008, 224 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 225 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 226 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 227 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 228 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 229 .emif_rd_wr_exec_thresh = 0x80000405, 230 .emif_prio_class_serv_map = 0x80000001, 231 .emif_connect_id_serv_1_map = 0x80000094, 232 .emif_connect_id_serv_2_map = 0x00000000, 233 .emif_cos_config = 0x000FFFFF 234 }; 235 236 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 237 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 238 .sdram_config = 0x638413B2, 239 .ref_ctrl = 0x00000C30, 240 .sdram_tim1 = 0xEAAAD4DB, 241 .sdram_tim2 = 0x266B7FDA, 242 .sdram_tim3 = 0x107F8678, 243 .read_idle_ctrl = 0x00050000, 244 .zq_config = 0x50074BE4, 245 .temp_alert_config = 0x0, 246 .emif_ddr_phy_ctlr_1 = 0x0E004008, 247 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 248 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 249 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 250 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 251 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 252 .emif_rd_wr_exec_thresh = 0x80000405, 253 .emif_prio_class_serv_map = 0x80000001, 254 .emif_connect_id_serv_1_map = 0x80000094, 255 .emif_connect_id_serv_2_map = 0x00000000, 256 .emif_cos_config = 0x000FFFFF 257 }; 258 259 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 260 .sdram_config = 0x638413b2, 261 .sdram_config2 = 0x00000000, 262 .ref_ctrl = 0x00000c30, 263 .sdram_tim1 = 0xeaaad4db, 264 .sdram_tim2 = 0x266b7fda, 265 .sdram_tim3 = 0x107f8678, 266 .read_idle_ctrl = 0x00050000, 267 .zq_config = 0x50074be4, 268 .temp_alert_config = 0x0, 269 .emif_ddr_phy_ctlr_1 = 0x0e084008, 270 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 271 .emif_ddr_ext_phy_ctrl_2 = 0x89, 272 .emif_ddr_ext_phy_ctrl_3 = 0x90, 273 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 274 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 275 .emif_rd_wr_lvl_rmp_win = 0x0, 276 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 277 .emif_rd_wr_lvl_ctl = 0x00000000, 278 .emif_rd_wr_exec_thresh = 0x80000000, 279 .emif_prio_class_serv_map = 0x80000001, 280 .emif_connect_id_serv_1_map = 0x80000094, 281 .emif_connect_id_serv_2_map = 0x00000000, 282 .emif_cos_config = 0x000FFFFF 283 }; 284 285 /* 286 * get_sys_clk_index : returns the index of the sys_clk read from 287 * ctrl status register. This value is either 288 * read from efuse or sysboot pins. 289 */ 290 static u32 get_sys_clk_index(void) 291 { 292 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 293 u32 ind = readl(&ctrl->statusreg), src; 294 295 src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT; 296 if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */ 297 return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >> 298 CTRL_CRYSTAL_FREQ_SELECTION_SHIFT); 299 else /* Value read from SYS BOOT pins */ 300 return ((ind & CTRL_SYSBOOT_15_14_MASK) >> 301 CTRL_SYSBOOT_15_14_SHIFT); 302 } 303 304 const struct dpll_params *get_dpll_ddr_params(void) 305 { 306 int ind = get_sys_clk_index(); 307 308 if (board_is_eposevm()) 309 return &epos_evm_dpll_ddr[ind]; 310 else if (board_is_gpevm() || board_is_sk()) 311 return &gp_evm_dpll_ddr; 312 313 printf(" Board '%s' not supported\n", am43xx_board_name); 314 return NULL; 315 } 316 317 318 /* 319 * get_opp_offset: 320 * Returns the index for safest OPP of the device to boot. 321 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 322 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 323 * This data is read from dev_attribute register which is e-fused. 324 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 325 * OPP available. Lowest OPP starts with min_off. So returning the 326 * bit with rightmost '0'. 327 */ 328 static int get_opp_offset(int max_off, int min_off) 329 { 330 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 331 int opp, offset, i; 332 333 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 334 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 335 336 for (i = max_off; i >= min_off; i--) { 337 offset = opp & (1 << i); 338 if (!offset) 339 return i; 340 } 341 342 return min_off; 343 } 344 345 const struct dpll_params *get_dpll_mpu_params(void) 346 { 347 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 348 u32 ind = get_sys_clk_index(); 349 350 return &dpll_mpu[ind][opp]; 351 } 352 353 const struct dpll_params *get_dpll_core_params(void) 354 { 355 int ind = get_sys_clk_index(); 356 357 return &dpll_core[ind]; 358 } 359 360 const struct dpll_params *get_dpll_per_params(void) 361 { 362 int ind = get_sys_clk_index(); 363 364 return &dpll_per[ind]; 365 } 366 367 void scale_vcores(void) 368 { 369 const struct dpll_params *mpu_params; 370 int mpu_vdd; 371 struct am43xx_board_id header; 372 373 enable_i2c0_pin_mux(); 374 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 375 if (read_eeprom(&header) < 0) 376 puts("Could not get board ID.\n"); 377 378 /* Get the frequency */ 379 mpu_params = get_dpll_mpu_params(); 380 381 if (i2c_probe(TPS65218_CHIP_PM)) 382 return; 383 384 if (mpu_params->m == 1000) { 385 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 386 } else if (mpu_params->m == 600) { 387 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 388 } else { 389 puts("Unknown MPU clock, not scaling\n"); 390 return; 391 } 392 393 /* Set DCDC1 (CORE) voltage to 1.1V */ 394 if (tps65218_voltage_update(TPS65218_DCDC1, 395 TPS65218_DCDC_VOLT_SEL_1100MV)) { 396 puts("tps65218_voltage_update failure\n"); 397 return; 398 } 399 400 /* Set DCDC2 (MPU) voltage */ 401 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 402 puts("tps65218_voltage_update failure\n"); 403 return; 404 } 405 } 406 407 void set_uart_mux_conf(void) 408 { 409 enable_uart0_pin_mux(); 410 } 411 412 void set_mux_conf_regs(void) 413 { 414 enable_board_pin_mux(); 415 } 416 417 static void enable_vtt_regulator(void) 418 { 419 u32 temp; 420 421 /* enable module */ 422 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 423 424 /* enable output for GPIO5_7 */ 425 writel(GPIO_SETDATAOUT(7), 426 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 427 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 428 temp = temp & ~(GPIO_OE_ENABLE(7)); 429 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 430 } 431 432 void sdram_init(void) 433 { 434 /* 435 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 436 * GP EMV has 1GB DDR3 connected to EMIF 437 * along with VTT regulator. 438 */ 439 if (board_is_eposevm()) { 440 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 441 } else if (board_is_evm_14_or_later()) { 442 enable_vtt_regulator(); 443 config_ddr(0, &ioregs_ddr3, NULL, NULL, 444 &ddr3_emif_regs_400Mhz_production, 0); 445 } else if (board_is_evm_12_or_later()) { 446 enable_vtt_regulator(); 447 config_ddr(0, &ioregs_ddr3, NULL, NULL, 448 &ddr3_emif_regs_400Mhz_beta, 0); 449 } else if (board_is_gpevm()) { 450 enable_vtt_regulator(); 451 config_ddr(0, &ioregs_ddr3, NULL, NULL, 452 &ddr3_emif_regs_400Mhz, 0); 453 } else if (board_is_sk()) { 454 config_ddr(400, &ioregs_ddr3, NULL, NULL, 455 &ddr3_sk_emif_regs_400Mhz, 0); 456 } 457 } 458 #endif 459 460 /* setup board specific PMIC */ 461 int power_init_board(void) 462 { 463 struct pmic *p; 464 465 power_tps65218_init(I2C_PMIC); 466 p = pmic_get("TPS65218_PMIC"); 467 if (p && !pmic_probe(p)) 468 puts("PMIC: TPS65218\n"); 469 470 return 0; 471 } 472 473 int board_init(void) 474 { 475 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 476 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 477 modena_init0_bw_integer, modena_init0_watermark_0; 478 479 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 480 gpmc_init(); 481 482 /* Clear all important bits for DSS errata that may need to be tweaked*/ 483 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 484 MREQPRIO_0_SAB_INIT0_MASK; 485 486 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 487 488 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 489 BW_LIMITER_BW_FRAC_MASK; 490 491 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 492 BW_LIMITER_BW_INT_MASK; 493 494 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 495 BW_LIMITER_BW_WATERMARK_MASK; 496 497 /* Setting MReq Priority of the DSS*/ 498 mreqprio_0 |= 0x77; 499 500 /* 501 * Set L3 Fast Configuration Register 502 * Limiting bandwith for ARM core to 700 MBPS 503 */ 504 modena_init0_bw_fractional |= 0x10; 505 modena_init0_bw_integer |= 0x3; 506 507 writel(mreqprio_0, &cdev->mreqprio_0); 508 writel(mreqprio_1, &cdev->mreqprio_1); 509 510 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 511 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 512 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 513 514 return 0; 515 } 516 517 #ifdef CONFIG_BOARD_LATE_INIT 518 int board_late_init(void) 519 { 520 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 521 char safe_string[HDR_NAME_LEN + 1]; 522 struct am43xx_board_id header; 523 524 if (read_eeprom(&header) < 0) 525 puts("Could not get board ID.\n"); 526 527 /* Now set variables based on the header. */ 528 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 529 safe_string[sizeof(header.name)] = 0; 530 setenv("board_name", safe_string); 531 532 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 533 safe_string[sizeof(header.version)] = 0; 534 setenv("board_rev", safe_string); 535 #endif 536 return 0; 537 } 538 #endif 539 540 #ifdef CONFIG_DRIVER_TI_CPSW 541 542 static void cpsw_control(int enabled) 543 { 544 /* Additional controls can be added here */ 545 return; 546 } 547 548 static struct cpsw_slave_data cpsw_slaves[] = { 549 { 550 .slave_reg_ofs = 0x208, 551 .sliver_reg_ofs = 0xd80, 552 .phy_addr = 16, 553 }, 554 { 555 .slave_reg_ofs = 0x308, 556 .sliver_reg_ofs = 0xdc0, 557 .phy_addr = 1, 558 }, 559 }; 560 561 static struct cpsw_platform_data cpsw_data = { 562 .mdio_base = CPSW_MDIO_BASE, 563 .cpsw_base = CPSW_BASE, 564 .mdio_div = 0xff, 565 .channels = 8, 566 .cpdma_reg_ofs = 0x800, 567 .slaves = 1, 568 .slave_data = cpsw_slaves, 569 .ale_reg_ofs = 0xd00, 570 .ale_entries = 1024, 571 .host_port_reg_ofs = 0x108, 572 .hw_stats_reg_ofs = 0x900, 573 .bd_ram_ofs = 0x2000, 574 .mac_control = (1 << 5), 575 .control = cpsw_control, 576 .host_port_num = 0, 577 .version = CPSW_CTRL_VERSION_2, 578 }; 579 580 int board_eth_init(bd_t *bis) 581 { 582 int rv; 583 uint8_t mac_addr[6]; 584 uint32_t mac_hi, mac_lo; 585 586 /* try reading mac address from efuse */ 587 mac_lo = readl(&cdev->macid0l); 588 mac_hi = readl(&cdev->macid0h); 589 mac_addr[0] = mac_hi & 0xFF; 590 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 591 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 592 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 593 mac_addr[4] = mac_lo & 0xFF; 594 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 595 596 if (!getenv("ethaddr")) { 597 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 598 if (is_valid_ether_addr(mac_addr)) 599 eth_setenv_enetaddr("ethaddr", mac_addr); 600 } 601 602 mac_lo = readl(&cdev->macid1l); 603 mac_hi = readl(&cdev->macid1h); 604 mac_addr[0] = mac_hi & 0xFF; 605 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 606 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 607 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 608 mac_addr[4] = mac_lo & 0xFF; 609 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 610 611 if (!getenv("eth1addr")) { 612 if (is_valid_ether_addr(mac_addr)) 613 eth_setenv_enetaddr("eth1addr", mac_addr); 614 } 615 616 if (board_is_eposevm()) { 617 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 618 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 619 cpsw_slaves[0].phy_addr = 16; 620 } else if (board_is_sk()) { 621 writel(RGMII_MODE_ENABLE, &cdev->miisel); 622 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 623 cpsw_slaves[0].phy_addr = 4; 624 cpsw_slaves[1].phy_addr = 5; 625 } else { 626 writel(RGMII_MODE_ENABLE, &cdev->miisel); 627 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 628 cpsw_slaves[0].phy_addr = 0; 629 } 630 631 rv = cpsw_register(&cpsw_data); 632 if (rv < 0) 633 printf("Error %d registering CPSW switch\n", rv); 634 635 return rv; 636 } 637 #endif 638