1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <linux/errno.h> 14 #include <spl.h> 15 #include <usb.h> 16 #include <asm/omap_sec_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/arch/mux.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/emif.h> 23 #include <asm/omap_common.h> 24 #include "../common/board_detect.h" 25 #include "board.h" 26 #include <power/pmic.h> 27 #include <power/tps65218.h> 28 #include <power/tps62362.h> 29 #include <miiphy.h> 30 #include <cpsw.h> 31 #include <linux/usb/gadget.h> 32 #include <dwc3-uboot.h> 33 #include <dwc3-omap-uboot.h> 34 #include <ti-usb-phy-uboot.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 39 40 /* 41 * Read header information from EEPROM into global structure. 42 */ 43 #ifdef CONFIG_TI_I2C_BOARD_DETECT 44 void do_board_detect(void) 45 { 46 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 47 CONFIG_EEPROM_CHIP_ADDRESS)) 48 printf("ti_i2c_eeprom_init failed\n"); 49 } 50 #endif 51 52 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 53 54 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 55 { /* 19.2 MHz */ 56 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 57 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 58 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 59 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 60 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 61 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 62 }, 63 { /* 24 MHz */ 64 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 65 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 66 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 67 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 68 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 69 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 70 }, 71 { /* 25 MHz */ 72 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 73 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 74 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 75 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 76 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 77 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 78 }, 79 { /* 26 MHz */ 80 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 81 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 82 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 83 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 84 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 85 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 86 }, 87 }; 88 89 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 90 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 91 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 92 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 93 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 94 }; 95 96 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 97 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 98 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 99 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 100 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 101 }; 102 103 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 104 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 105 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 106 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 107 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 108 }; 109 110 const struct dpll_params gp_evm_dpll_ddr = { 111 50, 2, 1, -1, 2, -1, -1}; 112 113 static const struct dpll_params idk_dpll_ddr = { 114 400, 23, 1, -1, 2, -1, -1 115 }; 116 117 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 118 0x00500050, 119 0x00350035, 120 0x00350035, 121 0x00350035, 122 0x00350035, 123 0x00350035, 124 0x00000000, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x00000000, 135 0x00000000, 136 0x40001000, 137 0x08102040 138 }; 139 140 const struct ctrl_ioregs ioregs_lpddr2 = { 141 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 142 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 143 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 144 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 145 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 148 .emif_sdram_config_ext = 0x1, 149 }; 150 151 const struct emif_regs emif_regs_lpddr2 = { 152 .sdram_config = 0x808012BA, 153 .ref_ctrl = 0x0000040D, 154 .sdram_tim1 = 0xEA86B411, 155 .sdram_tim2 = 0x103A094A, 156 .sdram_tim3 = 0x0F6BA37F, 157 .read_idle_ctrl = 0x00050000, 158 .zq_config = 0x50074BE4, 159 .temp_alert_config = 0x0, 160 .emif_rd_wr_lvl_rmp_win = 0x0, 161 .emif_rd_wr_lvl_rmp_ctl = 0x0, 162 .emif_rd_wr_lvl_ctl = 0x0, 163 .emif_ddr_phy_ctlr_1 = 0x0E284006, 164 .emif_rd_wr_exec_thresh = 0x80000405, 165 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 166 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 167 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 169 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 170 .emif_prio_class_serv_map = 0x80000001, 171 .emif_connect_id_serv_1_map = 0x80000094, 172 .emif_connect_id_serv_2_map = 0x00000000, 173 .emif_cos_config = 0x000FFFFF 174 }; 175 176 const struct ctrl_ioregs ioregs_ddr3 = { 177 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 178 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 179 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 180 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 181 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 183 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 184 .emif_sdram_config_ext = 0xc163, 185 }; 186 187 const struct emif_regs ddr3_emif_regs_400Mhz = { 188 .sdram_config = 0x638413B2, 189 .ref_ctrl = 0x00000C30, 190 .sdram_tim1 = 0xEAAAD4DB, 191 .sdram_tim2 = 0x266B7FDA, 192 .sdram_tim3 = 0x107F8678, 193 .read_idle_ctrl = 0x00050000, 194 .zq_config = 0x50074BE4, 195 .temp_alert_config = 0x0, 196 .emif_ddr_phy_ctlr_1 = 0x0E004008, 197 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 198 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 199 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 201 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 202 .emif_rd_wr_lvl_rmp_win = 0x0, 203 .emif_rd_wr_lvl_rmp_ctl = 0x0, 204 .emif_rd_wr_lvl_ctl = 0x0, 205 .emif_rd_wr_exec_thresh = 0x80000405, 206 .emif_prio_class_serv_map = 0x80000001, 207 .emif_connect_id_serv_1_map = 0x80000094, 208 .emif_connect_id_serv_2_map = 0x00000000, 209 .emif_cos_config = 0x000FFFFF 210 }; 211 212 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 213 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 214 .sdram_config = 0x638413B2, 215 .ref_ctrl = 0x00000C30, 216 .sdram_tim1 = 0xEAAAD4DB, 217 .sdram_tim2 = 0x266B7FDA, 218 .sdram_tim3 = 0x107F8678, 219 .read_idle_ctrl = 0x00050000, 220 .zq_config = 0x50074BE4, 221 .temp_alert_config = 0x0, 222 .emif_ddr_phy_ctlr_1 = 0x0E004008, 223 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 224 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 225 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 226 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 227 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 228 .emif_rd_wr_exec_thresh = 0x80000405, 229 .emif_prio_class_serv_map = 0x80000001, 230 .emif_connect_id_serv_1_map = 0x80000094, 231 .emif_connect_id_serv_2_map = 0x00000000, 232 .emif_cos_config = 0x000FFFFF 233 }; 234 235 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 236 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 237 .sdram_config = 0x638413B2, 238 .ref_ctrl = 0x00000C30, 239 .sdram_tim1 = 0xEAAAD4DB, 240 .sdram_tim2 = 0x266B7FDA, 241 .sdram_tim3 = 0x107F8678, 242 .read_idle_ctrl = 0x00050000, 243 .zq_config = 0x50074BE4, 244 .temp_alert_config = 0x0, 245 .emif_ddr_phy_ctlr_1 = 0x0E004008, 246 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 247 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 248 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 249 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 250 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 251 .emif_rd_wr_exec_thresh = 0x80000405, 252 .emif_prio_class_serv_map = 0x80000001, 253 .emif_connect_id_serv_1_map = 0x80000094, 254 .emif_connect_id_serv_2_map = 0x00000000, 255 .emif_cos_config = 0x000FFFFF 256 }; 257 258 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 259 .sdram_config = 0x638413b2, 260 .sdram_config2 = 0x00000000, 261 .ref_ctrl = 0x00000c30, 262 .sdram_tim1 = 0xeaaad4db, 263 .sdram_tim2 = 0x266b7fda, 264 .sdram_tim3 = 0x107f8678, 265 .read_idle_ctrl = 0x00050000, 266 .zq_config = 0x50074be4, 267 .temp_alert_config = 0x0, 268 .emif_ddr_phy_ctlr_1 = 0x0e084008, 269 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 270 .emif_ddr_ext_phy_ctrl_2 = 0x89, 271 .emif_ddr_ext_phy_ctrl_3 = 0x90, 272 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 273 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 274 .emif_rd_wr_lvl_rmp_win = 0x0, 275 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 276 .emif_rd_wr_lvl_ctl = 0x00000000, 277 .emif_rd_wr_exec_thresh = 0x80000000, 278 .emif_prio_class_serv_map = 0x80000001, 279 .emif_connect_id_serv_1_map = 0x80000094, 280 .emif_connect_id_serv_2_map = 0x00000000, 281 .emif_cos_config = 0x000FFFFF 282 }; 283 284 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 285 .sdram_config = 0x61a11b32, 286 .sdram_config2 = 0x00000000, 287 .ref_ctrl = 0x00000c30, 288 .sdram_tim1 = 0xeaaad4db, 289 .sdram_tim2 = 0x266b7fda, 290 .sdram_tim3 = 0x107f8678, 291 .read_idle_ctrl = 0x00050000, 292 .zq_config = 0x50074be4, 293 .temp_alert_config = 0x00000000, 294 .emif_ddr_phy_ctlr_1 = 0x00008009, 295 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 296 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 297 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 298 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 299 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 300 .emif_rd_wr_lvl_rmp_win = 0x00000000, 301 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 302 .emif_rd_wr_lvl_ctl = 0x00000000, 303 .emif_rd_wr_exec_thresh = 0x00000405, 304 .emif_prio_class_serv_map = 0x00000000, 305 .emif_connect_id_serv_1_map = 0x00000000, 306 .emif_connect_id_serv_2_map = 0x00000000, 307 .emif_cos_config = 0x00ffffff 308 }; 309 310 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 311 { 312 if (board_is_eposevm()) { 313 *regs = ext_phy_ctrl_const_base_lpddr2; 314 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 315 } 316 317 return; 318 } 319 320 const struct dpll_params *get_dpll_ddr_params(void) 321 { 322 int ind = get_sys_clk_index(); 323 324 if (board_is_eposevm()) 325 return &epos_evm_dpll_ddr[ind]; 326 else if (board_is_evm() || board_is_sk()) 327 return &gp_evm_dpll_ddr; 328 else if (board_is_idk()) 329 return &idk_dpll_ddr; 330 331 printf(" Board '%s' not supported\n", board_ti_get_name()); 332 return NULL; 333 } 334 335 336 /* 337 * get_opp_offset: 338 * Returns the index for safest OPP of the device to boot. 339 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 340 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 341 * This data is read from dev_attribute register which is e-fused. 342 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 343 * OPP available. Lowest OPP starts with min_off. So returning the 344 * bit with rightmost '0'. 345 */ 346 static int get_opp_offset(int max_off, int min_off) 347 { 348 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 349 int opp, offset, i; 350 351 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 352 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 353 354 for (i = max_off; i >= min_off; i--) { 355 offset = opp & (1 << i); 356 if (!offset) 357 return i; 358 } 359 360 return min_off; 361 } 362 363 const struct dpll_params *get_dpll_mpu_params(void) 364 { 365 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 366 u32 ind = get_sys_clk_index(); 367 368 return &dpll_mpu[ind][opp]; 369 } 370 371 const struct dpll_params *get_dpll_core_params(void) 372 { 373 int ind = get_sys_clk_index(); 374 375 return &dpll_core[ind]; 376 } 377 378 const struct dpll_params *get_dpll_per_params(void) 379 { 380 int ind = get_sys_clk_index(); 381 382 return &dpll_per[ind]; 383 } 384 385 void scale_vcores_generic(u32 m) 386 { 387 int mpu_vdd; 388 389 if (i2c_probe(TPS65218_CHIP_PM)) 390 return; 391 392 switch (m) { 393 case 1000: 394 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 395 break; 396 case 800: 397 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 398 break; 399 case 720: 400 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 401 break; 402 case 600: 403 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 404 break; 405 case 300: 406 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 407 break; 408 default: 409 puts("Unknown MPU clock, not scaling\n"); 410 return; 411 } 412 413 /* Set DCDC1 (CORE) voltage to 1.1V */ 414 if (tps65218_voltage_update(TPS65218_DCDC1, 415 TPS65218_DCDC_VOLT_SEL_1100MV)) { 416 printf("%s failure\n", __func__); 417 return; 418 } 419 420 /* Set DCDC2 (MPU) voltage */ 421 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 422 printf("%s failure\n", __func__); 423 return; 424 } 425 } 426 427 void scale_vcores_idk(u32 m) 428 { 429 int mpu_vdd; 430 431 if (i2c_probe(TPS62362_I2C_ADDR)) 432 return; 433 434 switch (m) { 435 case 1000: 436 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 437 break; 438 case 800: 439 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 440 break; 441 case 720: 442 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 443 break; 444 case 600: 445 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 446 break; 447 case 300: 448 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 449 break; 450 default: 451 puts("Unknown MPU clock, not scaling\n"); 452 return; 453 } 454 455 /* Set VDD_MPU voltage */ 456 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 457 printf("%s failure\n", __func__); 458 return; 459 } 460 } 461 462 void gpi2c_init(void) 463 { 464 /* When needed to be invoked prior to BSS initialization */ 465 static bool first_time = true; 466 467 if (first_time) { 468 enable_i2c0_pin_mux(); 469 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 470 CONFIG_SYS_OMAP24_I2C_SLAVE); 471 first_time = false; 472 } 473 } 474 475 void scale_vcores(void) 476 { 477 const struct dpll_params *mpu_params; 478 479 /* Ensure I2C is initialized for PMIC configuration */ 480 gpi2c_init(); 481 482 /* Get the frequency */ 483 mpu_params = get_dpll_mpu_params(); 484 485 if (board_is_idk()) 486 scale_vcores_idk(mpu_params->m); 487 else 488 scale_vcores_generic(mpu_params->m); 489 } 490 491 void set_uart_mux_conf(void) 492 { 493 enable_uart0_pin_mux(); 494 } 495 496 void set_mux_conf_regs(void) 497 { 498 enable_board_pin_mux(); 499 } 500 501 static void enable_vtt_regulator(void) 502 { 503 u32 temp; 504 505 /* enable module */ 506 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 507 508 /* enable output for GPIO5_7 */ 509 writel(GPIO_SETDATAOUT(7), 510 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 511 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 512 temp = temp & ~(GPIO_OE_ENABLE(7)); 513 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 514 } 515 516 void sdram_init(void) 517 { 518 /* 519 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 520 * GP EMV has 1GB DDR3 connected to EMIF 521 * along with VTT regulator. 522 */ 523 if (board_is_eposevm()) { 524 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 525 } else if (board_is_evm_14_or_later()) { 526 enable_vtt_regulator(); 527 config_ddr(0, &ioregs_ddr3, NULL, NULL, 528 &ddr3_emif_regs_400Mhz_production, 0); 529 } else if (board_is_evm_12_or_later()) { 530 enable_vtt_regulator(); 531 config_ddr(0, &ioregs_ddr3, NULL, NULL, 532 &ddr3_emif_regs_400Mhz_beta, 0); 533 } else if (board_is_evm()) { 534 enable_vtt_regulator(); 535 config_ddr(0, &ioregs_ddr3, NULL, NULL, 536 &ddr3_emif_regs_400Mhz, 0); 537 } else if (board_is_sk()) { 538 config_ddr(400, &ioregs_ddr3, NULL, NULL, 539 &ddr3_sk_emif_regs_400Mhz, 0); 540 } else if (board_is_idk()) { 541 config_ddr(400, &ioregs_ddr3, NULL, NULL, 542 &ddr3_idk_emif_regs_400Mhz, 0); 543 } 544 } 545 #endif 546 547 /* setup board specific PMIC */ 548 int power_init_board(void) 549 { 550 struct pmic *p; 551 552 if (board_is_idk()) { 553 power_tps62362_init(I2C_PMIC); 554 p = pmic_get("TPS62362"); 555 if (p && !pmic_probe(p)) 556 puts("PMIC: TPS62362\n"); 557 } else { 558 power_tps65218_init(I2C_PMIC); 559 p = pmic_get("TPS65218_PMIC"); 560 if (p && !pmic_probe(p)) 561 puts("PMIC: TPS65218\n"); 562 } 563 564 return 0; 565 } 566 567 int board_init(void) 568 { 569 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 570 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 571 modena_init0_bw_integer, modena_init0_watermark_0; 572 573 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 574 gpmc_init(); 575 576 /* Clear all important bits for DSS errata that may need to be tweaked*/ 577 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 578 MREQPRIO_0_SAB_INIT0_MASK; 579 580 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 581 582 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 583 BW_LIMITER_BW_FRAC_MASK; 584 585 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 586 BW_LIMITER_BW_INT_MASK; 587 588 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 589 BW_LIMITER_BW_WATERMARK_MASK; 590 591 /* Setting MReq Priority of the DSS*/ 592 mreqprio_0 |= 0x77; 593 594 /* 595 * Set L3 Fast Configuration Register 596 * Limiting bandwith for ARM core to 700 MBPS 597 */ 598 modena_init0_bw_fractional |= 0x10; 599 modena_init0_bw_integer |= 0x3; 600 601 writel(mreqprio_0, &cdev->mreqprio_0); 602 writel(mreqprio_1, &cdev->mreqprio_1); 603 604 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 605 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 606 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 607 608 return 0; 609 } 610 611 #ifdef CONFIG_BOARD_LATE_INIT 612 int board_late_init(void) 613 { 614 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 615 set_board_info_env(NULL); 616 617 /* 618 * Default FIT boot on HS devices. Non FIT images are not allowed 619 * on HS devices. 620 */ 621 if (get_device_type() == HS_DEVICE) 622 setenv("boot_fit", "1"); 623 #endif 624 return 0; 625 } 626 #endif 627 628 #ifdef CONFIG_USB_DWC3 629 static struct dwc3_device usb_otg_ss1 = { 630 .maximum_speed = USB_SPEED_HIGH, 631 .base = USB_OTG_SS1_BASE, 632 .tx_fifo_resize = false, 633 .index = 0, 634 }; 635 636 static struct dwc3_omap_device usb_otg_ss1_glue = { 637 .base = (void *)USB_OTG_SS1_GLUE_BASE, 638 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 639 .index = 0, 640 }; 641 642 static struct ti_usb_phy_device usb_phy1_device = { 643 .usb2_phy_power = (void *)USB2_PHY1_POWER, 644 .index = 0, 645 }; 646 647 static struct dwc3_device usb_otg_ss2 = { 648 .maximum_speed = USB_SPEED_HIGH, 649 .base = USB_OTG_SS2_BASE, 650 .tx_fifo_resize = false, 651 .index = 1, 652 }; 653 654 static struct dwc3_omap_device usb_otg_ss2_glue = { 655 .base = (void *)USB_OTG_SS2_GLUE_BASE, 656 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 657 .index = 1, 658 }; 659 660 static struct ti_usb_phy_device usb_phy2_device = { 661 .usb2_phy_power = (void *)USB2_PHY2_POWER, 662 .index = 1, 663 }; 664 665 int usb_gadget_handle_interrupts(int index) 666 { 667 u32 status; 668 669 status = dwc3_omap_uboot_interrupt_status(index); 670 if (status) 671 dwc3_uboot_handle_interrupt(index); 672 673 return 0; 674 } 675 #endif /* CONFIG_USB_DWC3 */ 676 677 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 678 int omap_xhci_board_usb_init(int index, enum usb_init_type init) 679 { 680 enable_usb_clocks(index); 681 #ifdef CONFIG_USB_DWC3 682 switch (index) { 683 case 0: 684 if (init == USB_INIT_DEVICE) { 685 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 686 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 687 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 688 ti_usb_phy_uboot_init(&usb_phy1_device); 689 dwc3_uboot_init(&usb_otg_ss1); 690 } 691 break; 692 case 1: 693 if (init == USB_INIT_DEVICE) { 694 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 695 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 696 ti_usb_phy_uboot_init(&usb_phy2_device); 697 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 698 dwc3_uboot_init(&usb_otg_ss2); 699 } 700 break; 701 default: 702 printf("Invalid Controller Index\n"); 703 } 704 #endif 705 706 return 0; 707 } 708 709 int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init) 710 { 711 #ifdef CONFIG_USB_DWC3 712 switch (index) { 713 case 0: 714 case 1: 715 if (init == USB_INIT_DEVICE) { 716 ti_usb_phy_uboot_exit(index); 717 dwc3_uboot_exit(index); 718 dwc3_omap_uboot_exit(index); 719 } 720 break; 721 default: 722 printf("Invalid Controller Index\n"); 723 } 724 #endif 725 disable_usb_clocks(index); 726 727 return 0; 728 } 729 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 730 731 #ifdef CONFIG_DRIVER_TI_CPSW 732 733 static void cpsw_control(int enabled) 734 { 735 /* Additional controls can be added here */ 736 return; 737 } 738 739 static struct cpsw_slave_data cpsw_slaves[] = { 740 { 741 .slave_reg_ofs = 0x208, 742 .sliver_reg_ofs = 0xd80, 743 .phy_addr = 16, 744 }, 745 { 746 .slave_reg_ofs = 0x308, 747 .sliver_reg_ofs = 0xdc0, 748 .phy_addr = 1, 749 }, 750 }; 751 752 static struct cpsw_platform_data cpsw_data = { 753 .mdio_base = CPSW_MDIO_BASE, 754 .cpsw_base = CPSW_BASE, 755 .mdio_div = 0xff, 756 .channels = 8, 757 .cpdma_reg_ofs = 0x800, 758 .slaves = 1, 759 .slave_data = cpsw_slaves, 760 .ale_reg_ofs = 0xd00, 761 .ale_entries = 1024, 762 .host_port_reg_ofs = 0x108, 763 .hw_stats_reg_ofs = 0x900, 764 .bd_ram_ofs = 0x2000, 765 .mac_control = (1 << 5), 766 .control = cpsw_control, 767 .host_port_num = 0, 768 .version = CPSW_CTRL_VERSION_2, 769 }; 770 771 int board_eth_init(bd_t *bis) 772 { 773 int rv; 774 uint8_t mac_addr[6]; 775 uint32_t mac_hi, mac_lo; 776 777 /* try reading mac address from efuse */ 778 mac_lo = readl(&cdev->macid0l); 779 mac_hi = readl(&cdev->macid0h); 780 mac_addr[0] = mac_hi & 0xFF; 781 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 782 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 783 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 784 mac_addr[4] = mac_lo & 0xFF; 785 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 786 787 if (!getenv("ethaddr")) { 788 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 789 if (is_valid_ethaddr(mac_addr)) 790 eth_setenv_enetaddr("ethaddr", mac_addr); 791 } 792 793 mac_lo = readl(&cdev->macid1l); 794 mac_hi = readl(&cdev->macid1h); 795 mac_addr[0] = mac_hi & 0xFF; 796 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 797 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 798 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 799 mac_addr[4] = mac_lo & 0xFF; 800 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 801 802 if (!getenv("eth1addr")) { 803 if (is_valid_ethaddr(mac_addr)) 804 eth_setenv_enetaddr("eth1addr", mac_addr); 805 } 806 807 if (board_is_eposevm()) { 808 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 809 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 810 cpsw_slaves[0].phy_addr = 16; 811 } else if (board_is_sk()) { 812 writel(RGMII_MODE_ENABLE, &cdev->miisel); 813 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 814 cpsw_slaves[0].phy_addr = 4; 815 cpsw_slaves[1].phy_addr = 5; 816 } else if (board_is_idk()) { 817 writel(RGMII_MODE_ENABLE, &cdev->miisel); 818 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 819 cpsw_slaves[0].phy_addr = 0; 820 } else { 821 writel(RGMII_MODE_ENABLE, &cdev->miisel); 822 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 823 cpsw_slaves[0].phy_addr = 0; 824 } 825 826 rv = cpsw_register(&cpsw_data); 827 if (rv < 0) 828 printf("Error %d registering CPSW switch\n", rv); 829 830 return rv; 831 } 832 #endif 833 834 #ifdef CONFIG_SPL_LOAD_FIT 835 int board_fit_config_name_match(const char *name) 836 { 837 if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 838 return 0; 839 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 840 return 0; 841 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 842 return 0; 843 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 844 return 0; 845 else 846 return -1; 847 } 848 #endif 849 850 #ifdef CONFIG_TI_SECURE_DEVICE 851 void board_fit_image_post_process(void **p_image, size_t *p_size) 852 { 853 secure_boot_verify_image(p_image, p_size); 854 } 855 #endif 856