1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/ddr_defs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include <power/tps65217.h> 30 #include <power/tps65910.h> 31 #include <environment.h> 32 #include <watchdog.h> 33 #include <environment.h> 34 #include "../common/board_detect.h" 35 #include "board.h" 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 /* GPIO that controls power to DDR on EVM-SK */ 40 #define GPIO_DDR_VTT_EN 7 41 #define ICE_GPIO_DDR_VTT_EN 18 42 43 #if defined(CONFIG_SPL_BUILD) || \ 44 (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH)) 45 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 46 #endif 47 48 /* 49 * Read header information from EEPROM into global structure. 50 */ 51 static inline int __maybe_unused read_eeprom(void) 52 { 53 return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR); 54 } 55 56 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 57 static const struct ddr_data ddr2_data = { 58 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 59 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 60 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 61 }; 62 63 static const struct cmd_control ddr2_cmd_ctrl_data = { 64 .cmd0csratio = MT47H128M16RT25E_RATIO, 65 66 .cmd1csratio = MT47H128M16RT25E_RATIO, 67 68 .cmd2csratio = MT47H128M16RT25E_RATIO, 69 }; 70 71 static const struct emif_regs ddr2_emif_reg_data = { 72 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 73 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 74 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 75 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 76 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 77 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 78 }; 79 80 static const struct ddr_data ddr3_data = { 81 .datardsratio0 = MT41J128MJT125_RD_DQS, 82 .datawdsratio0 = MT41J128MJT125_WR_DQS, 83 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 84 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 85 }; 86 87 static const struct ddr_data ddr3_beagleblack_data = { 88 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 89 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 90 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 91 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 92 }; 93 94 static const struct ddr_data ddr3_evm_data = { 95 .datardsratio0 = MT41J512M8RH125_RD_DQS, 96 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 97 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 98 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 99 }; 100 101 static const struct ddr_data ddr3_icev2_data = { 102 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 103 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 104 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 105 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 106 }; 107 108 static const struct cmd_control ddr3_cmd_ctrl_data = { 109 .cmd0csratio = MT41J128MJT125_RATIO, 110 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 111 112 .cmd1csratio = MT41J128MJT125_RATIO, 113 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 114 115 .cmd2csratio = MT41J128MJT125_RATIO, 116 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 117 }; 118 119 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 120 .cmd0csratio = MT41K256M16HA125E_RATIO, 121 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 122 123 .cmd1csratio = MT41K256M16HA125E_RATIO, 124 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 125 126 .cmd2csratio = MT41K256M16HA125E_RATIO, 127 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 128 }; 129 130 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 131 .cmd0csratio = MT41J512M8RH125_RATIO, 132 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 133 134 .cmd1csratio = MT41J512M8RH125_RATIO, 135 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 136 137 .cmd2csratio = MT41J512M8RH125_RATIO, 138 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 139 }; 140 141 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 142 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 143 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 144 145 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 146 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 147 148 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 149 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 150 }; 151 152 static struct emif_regs ddr3_emif_reg_data = { 153 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 154 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 155 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 156 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 157 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 158 .zq_config = MT41J128MJT125_ZQ_CFG, 159 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 160 PHY_EN_DYN_PWRDN, 161 }; 162 163 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 164 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 165 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 166 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 167 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 168 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 169 .zq_config = MT41K256M16HA125E_ZQ_CFG, 170 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 171 }; 172 173 static struct emif_regs ddr3_evm_emif_reg_data = { 174 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 175 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 176 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 177 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 178 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 179 .zq_config = MT41J512M8RH125_ZQ_CFG, 180 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 181 PHY_EN_DYN_PWRDN, 182 }; 183 184 static struct emif_regs ddr3_icev2_emif_reg_data = { 185 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 186 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 187 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 188 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 189 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 190 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 191 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 192 PHY_EN_DYN_PWRDN, 193 }; 194 195 #ifdef CONFIG_SPL_OS_BOOT 196 int spl_start_uboot(void) 197 { 198 /* break into full u-boot on 'c' */ 199 if (serial_tstc() && serial_getc() == 'c') 200 return 1; 201 202 #ifdef CONFIG_SPL_ENV_SUPPORT 203 env_init(); 204 env_relocate_spec(); 205 if (getenv_yesno("boot_os") != 1) 206 return 1; 207 #endif 208 209 return 0; 210 } 211 #endif 212 213 #define OSC (V_OSCK/1000000) 214 const struct dpll_params dpll_ddr = { 215 266, OSC-1, 1, -1, -1, -1, -1}; 216 const struct dpll_params dpll_ddr_evm_sk = { 217 303, OSC-1, 1, -1, -1, -1, -1}; 218 const struct dpll_params dpll_ddr_bone_black = { 219 400, OSC-1, 1, -1, -1, -1, -1}; 220 221 void am33xx_spl_board_init(void) 222 { 223 int mpu_vdd; 224 225 if (read_eeprom() < 0) 226 puts("Could not get board ID.\n"); 227 228 /* Get the frequency */ 229 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 230 231 if (board_is_bone() || board_is_bone_lt()) { 232 /* BeagleBone PMIC Code */ 233 int usb_cur_lim; 234 235 /* 236 * Only perform PMIC configurations if board rev > A1 237 * on Beaglebone White 238 */ 239 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 240 return; 241 242 if (i2c_probe(TPS65217_CHIP_PM)) 243 return; 244 245 /* 246 * On Beaglebone White we need to ensure we have AC power 247 * before increasing the frequency. 248 */ 249 if (board_is_bone()) { 250 uchar pmic_status_reg; 251 if (tps65217_reg_read(TPS65217_STATUS, 252 &pmic_status_reg)) 253 return; 254 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 255 puts("No AC power, disabling frequency switch\n"); 256 return; 257 } 258 } 259 260 /* 261 * Override what we have detected since we know if we have 262 * a Beaglebone Black it supports 1GHz. 263 */ 264 if (board_is_bone_lt()) 265 dpll_mpu_opp100.m = MPUPLL_M_1000; 266 267 /* 268 * Increase USB current limit to 1300mA or 1800mA and set 269 * the MPU voltage controller as needed. 270 */ 271 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 272 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 273 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 274 } else { 275 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 276 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 277 } 278 279 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 280 TPS65217_POWER_PATH, 281 usb_cur_lim, 282 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 283 puts("tps65217_reg_write failure\n"); 284 285 /* Set DCDC3 (CORE) voltage to 1.125V */ 286 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 287 TPS65217_DCDC_VOLT_SEL_1125MV)) { 288 puts("tps65217_voltage_update failure\n"); 289 return; 290 } 291 292 /* Set CORE Frequencies to OPP100 */ 293 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 294 295 /* Set DCDC2 (MPU) voltage */ 296 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 297 puts("tps65217_voltage_update failure\n"); 298 return; 299 } 300 301 /* 302 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 303 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 304 */ 305 if (board_is_bone()) { 306 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 307 TPS65217_DEFLS1, 308 TPS65217_LDO_VOLTAGE_OUT_3_3, 309 TPS65217_LDO_MASK)) 310 puts("tps65217_reg_write failure\n"); 311 } else { 312 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 313 TPS65217_DEFLS1, 314 TPS65217_LDO_VOLTAGE_OUT_1_8, 315 TPS65217_LDO_MASK)) 316 puts("tps65217_reg_write failure\n"); 317 } 318 319 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 320 TPS65217_DEFLS2, 321 TPS65217_LDO_VOLTAGE_OUT_3_3, 322 TPS65217_LDO_MASK)) 323 puts("tps65217_reg_write failure\n"); 324 } else { 325 int sil_rev; 326 327 /* 328 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 329 * MPU frequencies we support we use a CORE voltage of 330 * 1.1375V. For MPU voltage we need to switch based on 331 * the frequency we are running at. 332 */ 333 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 334 return; 335 336 /* 337 * Depending on MPU clock and PG we will need a different 338 * VDD to drive at that speed. 339 */ 340 sil_rev = readl(&cdev->deviceid) >> 28; 341 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 342 dpll_mpu_opp100.m); 343 344 /* Tell the TPS65910 to use i2c */ 345 tps65910_set_i2c_control(); 346 347 /* First update MPU voltage. */ 348 if (tps65910_voltage_update(MPU, mpu_vdd)) 349 return; 350 351 /* Second, update the CORE voltage. */ 352 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 353 return; 354 355 /* Set CORE Frequencies to OPP100 */ 356 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 357 } 358 359 /* Set MPU Frequency to what we detected now that voltages are set */ 360 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 361 } 362 363 const struct dpll_params *get_dpll_ddr_params(void) 364 { 365 enable_i2c0_pin_mux(); 366 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 367 if (read_eeprom() < 0) 368 puts("Could not get board ID.\n"); 369 370 if (board_is_evm_sk()) 371 return &dpll_ddr_evm_sk; 372 else if (board_is_bone_lt() || board_is_icev2()) 373 return &dpll_ddr_bone_black; 374 else if (board_is_evm_15_or_later()) 375 return &dpll_ddr_evm_sk; 376 else 377 return &dpll_ddr; 378 } 379 380 void set_uart_mux_conf(void) 381 { 382 #if CONFIG_CONS_INDEX == 1 383 enable_uart0_pin_mux(); 384 #elif CONFIG_CONS_INDEX == 2 385 enable_uart1_pin_mux(); 386 #elif CONFIG_CONS_INDEX == 3 387 enable_uart2_pin_mux(); 388 #elif CONFIG_CONS_INDEX == 4 389 enable_uart3_pin_mux(); 390 #elif CONFIG_CONS_INDEX == 5 391 enable_uart4_pin_mux(); 392 #elif CONFIG_CONS_INDEX == 6 393 enable_uart5_pin_mux(); 394 #endif 395 } 396 397 void set_mux_conf_regs(void) 398 { 399 if (read_eeprom() < 0) 400 puts("Could not get board ID.\n"); 401 402 enable_board_pin_mux(); 403 } 404 405 const struct ctrl_ioregs ioregs_evmsk = { 406 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 407 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 408 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 409 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 410 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 411 }; 412 413 const struct ctrl_ioregs ioregs_bonelt = { 414 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 415 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 416 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 417 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 418 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 419 }; 420 421 const struct ctrl_ioregs ioregs_evm15 = { 422 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 423 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 424 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 425 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 426 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 427 }; 428 429 const struct ctrl_ioregs ioregs = { 430 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 431 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 432 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 433 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 434 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 435 }; 436 437 void sdram_init(void) 438 { 439 if (read_eeprom() < 0) 440 puts("Could not get board ID.\n"); 441 442 if (board_is_evm_sk()) { 443 /* 444 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 445 * This is safe enough to do on older revs. 446 */ 447 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 448 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 449 } 450 451 if (board_is_icev2()) { 452 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 453 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 454 } 455 456 if (board_is_evm_sk()) 457 config_ddr(303, &ioregs_evmsk, &ddr3_data, 458 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 459 else if (board_is_bone_lt()) 460 config_ddr(400, &ioregs_bonelt, 461 &ddr3_beagleblack_data, 462 &ddr3_beagleblack_cmd_ctrl_data, 463 &ddr3_beagleblack_emif_reg_data, 0); 464 else if (board_is_evm_15_or_later()) 465 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 466 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 467 else if (board_is_icev2()) 468 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 469 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 470 0); 471 else 472 config_ddr(266, &ioregs, &ddr2_data, 473 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 474 } 475 #endif 476 477 /* 478 * Basic board specific setup. Pinmux has been handled already. 479 */ 480 int board_init(void) 481 { 482 #if defined(CONFIG_HW_WATCHDOG) 483 hw_watchdog_init(); 484 #endif 485 486 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 487 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 488 gpmc_init(); 489 #endif 490 return 0; 491 } 492 493 #ifdef CONFIG_BOARD_LATE_INIT 494 int board_late_init(void) 495 { 496 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 497 int rc; 498 char *name = NULL; 499 500 rc = read_eeprom(); 501 if (rc) 502 puts("Could not get board ID.\n"); 503 504 if (board_is_bbg1()) 505 name = "BBG1"; 506 set_board_info_env(name); 507 #endif 508 509 return 0; 510 } 511 #endif 512 513 #ifndef CONFIG_DM_ETH 514 515 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 516 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 517 static void cpsw_control(int enabled) 518 { 519 /* VTP can be added here */ 520 521 return; 522 } 523 524 static struct cpsw_slave_data cpsw_slaves[] = { 525 { 526 .slave_reg_ofs = 0x208, 527 .sliver_reg_ofs = 0xd80, 528 .phy_addr = 0, 529 }, 530 { 531 .slave_reg_ofs = 0x308, 532 .sliver_reg_ofs = 0xdc0, 533 .phy_addr = 1, 534 }, 535 }; 536 537 static struct cpsw_platform_data cpsw_data = { 538 .mdio_base = CPSW_MDIO_BASE, 539 .cpsw_base = CPSW_BASE, 540 .mdio_div = 0xff, 541 .channels = 8, 542 .cpdma_reg_ofs = 0x800, 543 .slaves = 1, 544 .slave_data = cpsw_slaves, 545 .ale_reg_ofs = 0xd00, 546 .ale_entries = 1024, 547 .host_port_reg_ofs = 0x108, 548 .hw_stats_reg_ofs = 0x900, 549 .bd_ram_ofs = 0x2000, 550 .mac_control = (1 << 5), 551 .control = cpsw_control, 552 .host_port_num = 0, 553 .version = CPSW_CTRL_VERSION_2, 554 }; 555 #endif 556 557 /* 558 * This function will: 559 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 560 * in the environment 561 * Perform fixups to the PHY present on certain boards. We only need this 562 * function in: 563 * - SPL with either CPSW or USB ethernet support 564 * - Full U-Boot, with either CPSW or USB ethernet 565 * Build in only these cases to avoid warnings about unused variables 566 * when we build an SPL that has neither option but full U-Boot will. 567 */ 568 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ 569 && defined(CONFIG_SPL_BUILD)) || \ 570 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 571 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ 572 !defined(CONFIG_SPL_BUILD)) 573 int board_eth_init(bd_t *bis) 574 { 575 int rv, n = 0; 576 uint8_t mac_addr[6]; 577 uint32_t mac_hi, mac_lo; 578 __maybe_unused struct ti_am_eeprom *header; 579 580 /* try reading mac address from efuse */ 581 mac_lo = readl(&cdev->macid0l); 582 mac_hi = readl(&cdev->macid0h); 583 mac_addr[0] = mac_hi & 0xFF; 584 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 585 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 586 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 587 mac_addr[4] = mac_lo & 0xFF; 588 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 589 590 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 591 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 592 if (!getenv("ethaddr")) { 593 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 594 595 if (is_valid_ethaddr(mac_addr)) 596 eth_setenv_enetaddr("ethaddr", mac_addr); 597 } 598 599 #ifdef CONFIG_DRIVER_TI_CPSW 600 601 mac_lo = readl(&cdev->macid1l); 602 mac_hi = readl(&cdev->macid1h); 603 mac_addr[0] = mac_hi & 0xFF; 604 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 605 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 606 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 607 mac_addr[4] = mac_lo & 0xFF; 608 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 609 610 if (!getenv("eth1addr")) { 611 if (is_valid_ethaddr(mac_addr)) 612 eth_setenv_enetaddr("eth1addr", mac_addr); 613 } 614 615 if (read_eeprom() < 0) 616 puts("Could not get board ID.\n"); 617 618 if (board_is_bone() || board_is_bone_lt() || 619 board_is_idk()) { 620 writel(MII_MODE_ENABLE, &cdev->miisel); 621 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 622 PHY_INTERFACE_MODE_MII; 623 } else { 624 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 625 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 626 PHY_INTERFACE_MODE_RGMII; 627 } 628 629 rv = cpsw_register(&cpsw_data); 630 if (rv < 0) 631 printf("Error %d registering CPSW switch\n", rv); 632 else 633 n += rv; 634 #endif 635 636 /* 637 * 638 * CPSW RGMII Internal Delay Mode is not supported in all PVT 639 * operating points. So we must set the TX clock delay feature 640 * in the AR8051 PHY. Since we only support a single ethernet 641 * device in U-Boot, we only do this for the first instance. 642 */ 643 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 644 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 645 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 646 #define AR8051_RGMII_TX_CLK_DLY 0x100 647 648 if (board_is_evm_sk() || board_is_gp_evm()) { 649 const char *devname; 650 devname = miiphy_get_current_dev(); 651 652 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 653 AR8051_DEBUG_RGMII_CLK_DLY_REG); 654 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 655 AR8051_RGMII_TX_CLK_DLY); 656 } 657 #endif 658 #if defined(CONFIG_USB_ETHER) && \ 659 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 660 if (is_valid_ethaddr(mac_addr)) 661 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 662 663 rv = usb_eth_initialize(bis); 664 if (rv < 0) 665 printf("Error %d registering USB_ETHER\n", rv); 666 else 667 n += rv; 668 #endif 669 return n; 670 } 671 #endif 672 673 #endif /* CONFIG_DM_ETH */ 674 675 #ifdef CONFIG_SPL_LOAD_FIT 676 int board_fit_config_name_match(const char *name) 677 { 678 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 679 return 0; 680 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 681 return 0; 682 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 683 return 0; 684 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 685 return 0; 686 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 687 return 0; 688 else 689 return -1; 690 } 691 #endif 692