1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/ddr_defs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/io.h> 23 #include <asm/emif.h> 24 #include <asm/gpio.h> 25 #include <i2c.h> 26 #include <miiphy.h> 27 #include <cpsw.h> 28 #include "board.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 33 34 /* MII mode defines */ 35 #define MII_MODE_ENABLE 0x0 36 #define RGMII_MODE_ENABLE 0x3A 37 38 /* GPIO that controls power to DDR on EVM-SK */ 39 #define GPIO_DDR_VTT_EN 7 40 41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 42 43 /* 44 * Read header information from EEPROM into global structure. 45 */ 46 static int read_eeprom(struct am335x_baseboard_id *header) 47 { 48 /* Check if baseboard eeprom is available */ 49 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 50 puts("Could not probe the EEPROM; something fundamentally " 51 "wrong on the I2C bus.\n"); 52 return -ENODEV; 53 } 54 55 /* read the eeprom using i2c */ 56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 57 sizeof(struct am335x_baseboard_id))) { 58 puts("Could not read the EEPROM; something fundamentally" 59 " wrong on the I2C bus.\n"); 60 return -EIO; 61 } 62 63 if (header->magic != 0xEE3355AA) { 64 /* 65 * read the eeprom using i2c again, 66 * but use only a 1 byte address 67 */ 68 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 69 sizeof(struct am335x_baseboard_id))) { 70 puts("Could not read the EEPROM; something " 71 "fundamentally wrong on the I2C bus.\n"); 72 return -EIO; 73 } 74 75 if (header->magic != 0xEE3355AA) { 76 printf("Incorrect magic number (0x%x) in EEPROM\n", 77 header->magic); 78 return -EINVAL; 79 } 80 } 81 82 return 0; 83 } 84 85 #ifdef CONFIG_SPL_BUILD 86 static const struct ddr_data ddr2_data = { 87 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 88 (MT47H128M16RT25E_RD_DQS<<20) | 89 (MT47H128M16RT25E_RD_DQS<<10) | 90 (MT47H128M16RT25E_RD_DQS<<0)), 91 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 92 (MT47H128M16RT25E_WR_DQS<<20) | 93 (MT47H128M16RT25E_WR_DQS<<10) | 94 (MT47H128M16RT25E_WR_DQS<<0)), 95 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 96 (MT47H128M16RT25E_PHY_WRLVL<<20) | 97 (MT47H128M16RT25E_PHY_WRLVL<<10) | 98 (MT47H128M16RT25E_PHY_WRLVL<<0)), 99 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 100 (MT47H128M16RT25E_PHY_GATELVL<<20) | 101 (MT47H128M16RT25E_PHY_GATELVL<<10) | 102 (MT47H128M16RT25E_PHY_GATELVL<<0)), 103 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 104 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 105 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 106 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 107 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 108 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 109 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 110 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 111 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 112 .datadldiff0 = PHY_DLL_LOCK_DIFF, 113 }; 114 115 static const struct cmd_control ddr2_cmd_ctrl_data = { 116 .cmd0csratio = MT47H128M16RT25E_RATIO, 117 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 118 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 119 120 .cmd1csratio = MT47H128M16RT25E_RATIO, 121 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 122 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 123 124 .cmd2csratio = MT47H128M16RT25E_RATIO, 125 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 126 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 127 }; 128 129 static const struct emif_regs ddr2_emif_reg_data = { 130 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 131 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 132 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 133 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 134 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 135 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 136 }; 137 138 static const struct ddr_data ddr3_data = { 139 .datardsratio0 = MT41J128MJT125_RD_DQS, 140 .datawdsratio0 = MT41J128MJT125_WR_DQS, 141 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 142 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 143 .datadldiff0 = PHY_DLL_LOCK_DIFF, 144 }; 145 146 static const struct ddr_data ddr3_beagleblack_data = { 147 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 148 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 149 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 150 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 151 .datadldiff0 = PHY_DLL_LOCK_DIFF, 152 }; 153 154 static const struct ddr_data ddr3_evm_data = { 155 .datardsratio0 = MT41J512M8RH125_RD_DQS, 156 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 157 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 158 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 159 .datadldiff0 = PHY_DLL_LOCK_DIFF, 160 }; 161 162 static const struct cmd_control ddr3_cmd_ctrl_data = { 163 .cmd0csratio = MT41J128MJT125_RATIO, 164 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 165 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 166 167 .cmd1csratio = MT41J128MJT125_RATIO, 168 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 169 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 170 171 .cmd2csratio = MT41J128MJT125_RATIO, 172 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 173 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 174 }; 175 176 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 177 .cmd0csratio = MT41K256M16HA125E_RATIO, 178 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 179 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 180 181 .cmd1csratio = MT41K256M16HA125E_RATIO, 182 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 183 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 184 185 .cmd2csratio = MT41K256M16HA125E_RATIO, 186 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 187 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 188 }; 189 190 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 191 .cmd0csratio = MT41J512M8RH125_RATIO, 192 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 193 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 194 195 .cmd1csratio = MT41J512M8RH125_RATIO, 196 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 197 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 198 199 .cmd2csratio = MT41J512M8RH125_RATIO, 200 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 201 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 202 }; 203 204 static struct emif_regs ddr3_emif_reg_data = { 205 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 206 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 207 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 208 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 209 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 210 .zq_config = MT41J128MJT125_ZQ_CFG, 211 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 212 PHY_EN_DYN_PWRDN, 213 }; 214 215 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 216 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 217 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 218 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 219 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 220 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 221 .zq_config = MT41K256M16HA125E_ZQ_CFG, 222 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 223 }; 224 225 static struct emif_regs ddr3_evm_emif_reg_data = { 226 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 227 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 228 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 229 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 230 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 231 .zq_config = MT41J512M8RH125_ZQ_CFG, 232 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 233 PHY_EN_DYN_PWRDN, 234 }; 235 236 #ifdef CONFIG_SPL_OS_BOOT 237 int spl_start_uboot(void) 238 { 239 /* break into full u-boot on 'c' */ 240 return (serial_tstc() && serial_getc() == 'c'); 241 } 242 #endif 243 244 #endif 245 246 /* 247 * early system init of muxing and clocks. 248 */ 249 void s_init(void) 250 { 251 #ifdef CONFIG_SPL_BUILD 252 struct am335x_baseboard_id header; 253 254 /* 255 * Save the boot parameters passed from romcode. 256 * We cannot delay the saving further than this, 257 * to prevent overwrites. 258 */ 259 save_omap_boot_params(); 260 #endif 261 262 /* WDT1 is already running when the bootloader gets control 263 * Disable it to avoid "random" resets 264 */ 265 writel(0xAAAA, &wdtimer->wdtwspr); 266 while (readl(&wdtimer->wdtwwps) != 0x0) 267 ; 268 writel(0x5555, &wdtimer->wdtwspr); 269 while (readl(&wdtimer->wdtwwps) != 0x0) 270 ; 271 272 #ifdef CONFIG_SPL_BUILD 273 /* Setup the PLLs and the clocks for the peripherals */ 274 pll_init(); 275 276 /* Enable RTC32K clock */ 277 rtc32k_enable(); 278 279 #ifdef CONFIG_SERIAL1 280 enable_uart0_pin_mux(); 281 #endif /* CONFIG_SERIAL1 */ 282 #ifdef CONFIG_SERIAL2 283 enable_uart1_pin_mux(); 284 #endif /* CONFIG_SERIAL2 */ 285 #ifdef CONFIG_SERIAL3 286 enable_uart2_pin_mux(); 287 #endif /* CONFIG_SERIAL3 */ 288 #ifdef CONFIG_SERIAL4 289 enable_uart3_pin_mux(); 290 #endif /* CONFIG_SERIAL4 */ 291 #ifdef CONFIG_SERIAL5 292 enable_uart4_pin_mux(); 293 #endif /* CONFIG_SERIAL5 */ 294 #ifdef CONFIG_SERIAL6 295 enable_uart5_pin_mux(); 296 #endif /* CONFIG_SERIAL6 */ 297 298 uart_soft_reset(); 299 300 gd = &gdata; 301 302 preloader_console_init(); 303 304 /* Initalize the board header */ 305 enable_i2c0_pin_mux(); 306 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 307 if (read_eeprom(&header) < 0) 308 puts("Could not get board ID.\n"); 309 310 enable_board_pin_mux(&header); 311 if (board_is_evm_sk(&header)) { 312 /* 313 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 314 * This is safe enough to do on older revs. 315 */ 316 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 317 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 318 } 319 320 if (board_is_evm_sk(&header)) 321 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 322 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 323 else if (board_is_bone_lt(&header)) 324 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 325 &ddr3_beagleblack_data, 326 &ddr3_beagleblack_cmd_ctrl_data, 327 &ddr3_beagleblack_emif_reg_data, 0); 328 else if (board_is_evm_15_or_later(&header)) 329 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 330 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 331 else 332 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 333 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 334 #endif 335 } 336 337 /* 338 * Basic board specific setup. Pinmux has been handled already. 339 */ 340 int board_init(void) 341 { 342 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 343 344 gpmc_init(); 345 346 return 0; 347 } 348 349 #ifdef CONFIG_BOARD_LATE_INIT 350 int board_late_init(void) 351 { 352 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 353 char safe_string[HDR_NAME_LEN + 1]; 354 struct am335x_baseboard_id header; 355 356 if (read_eeprom(&header) < 0) 357 puts("Could not get board ID.\n"); 358 359 /* Now set variables based on the header. */ 360 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 361 safe_string[sizeof(header.name)] = 0; 362 setenv("board_name", safe_string); 363 364 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 365 safe_string[sizeof(header.version)] = 0; 366 setenv("board_rev", safe_string); 367 #endif 368 369 return 0; 370 } 371 #endif 372 373 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 374 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 375 static void cpsw_control(int enabled) 376 { 377 /* VTP can be added here */ 378 379 return; 380 } 381 382 static struct cpsw_slave_data cpsw_slaves[] = { 383 { 384 .slave_reg_ofs = 0x208, 385 .sliver_reg_ofs = 0xd80, 386 .phy_id = 0, 387 }, 388 { 389 .slave_reg_ofs = 0x308, 390 .sliver_reg_ofs = 0xdc0, 391 .phy_id = 1, 392 }, 393 }; 394 395 static struct cpsw_platform_data cpsw_data = { 396 .mdio_base = CPSW_MDIO_BASE, 397 .cpsw_base = CPSW_BASE, 398 .mdio_div = 0xff, 399 .channels = 8, 400 .cpdma_reg_ofs = 0x800, 401 .slaves = 1, 402 .slave_data = cpsw_slaves, 403 .ale_reg_ofs = 0xd00, 404 .ale_entries = 1024, 405 .host_port_reg_ofs = 0x108, 406 .hw_stats_reg_ofs = 0x900, 407 .bd_ram_ofs = 0x2000, 408 .mac_control = (1 << 5), 409 .control = cpsw_control, 410 .host_port_num = 0, 411 .version = CPSW_CTRL_VERSION_2, 412 }; 413 #endif 414 415 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 416 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 417 int board_eth_init(bd_t *bis) 418 { 419 int rv, n = 0; 420 uint8_t mac_addr[6]; 421 uint32_t mac_hi, mac_lo; 422 __maybe_unused struct am335x_baseboard_id header; 423 424 /* try reading mac address from efuse */ 425 mac_lo = readl(&cdev->macid0l); 426 mac_hi = readl(&cdev->macid0h); 427 mac_addr[0] = mac_hi & 0xFF; 428 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 429 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 430 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 431 mac_addr[4] = mac_lo & 0xFF; 432 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 433 434 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 435 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 436 if (!getenv("ethaddr")) { 437 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 438 439 if (is_valid_ether_addr(mac_addr)) 440 eth_setenv_enetaddr("ethaddr", mac_addr); 441 } 442 443 #ifdef CONFIG_DRIVER_TI_CPSW 444 if (read_eeprom(&header) < 0) 445 puts("Could not get board ID.\n"); 446 447 if (board_is_bone(&header) || board_is_bone_lt(&header) || 448 board_is_idk(&header)) { 449 writel(MII_MODE_ENABLE, &cdev->miisel); 450 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 451 PHY_INTERFACE_MODE_MII; 452 } else { 453 writel(RGMII_MODE_ENABLE, &cdev->miisel); 454 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 455 PHY_INTERFACE_MODE_RGMII; 456 } 457 458 rv = cpsw_register(&cpsw_data); 459 if (rv < 0) 460 printf("Error %d registering CPSW switch\n", rv); 461 else 462 n += rv; 463 #endif 464 465 /* 466 * 467 * CPSW RGMII Internal Delay Mode is not supported in all PVT 468 * operating points. So we must set the TX clock delay feature 469 * in the AR8051 PHY. Since we only support a single ethernet 470 * device in U-Boot, we only do this for the first instance. 471 */ 472 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 473 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 474 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 475 #define AR8051_RGMII_TX_CLK_DLY 0x100 476 477 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 478 const char *devname; 479 devname = miiphy_get_current_dev(); 480 481 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 482 AR8051_DEBUG_RGMII_CLK_DLY_REG); 483 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 484 AR8051_RGMII_TX_CLK_DLY); 485 } 486 #endif 487 #if defined(CONFIG_USB_ETHER) && \ 488 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 489 if (is_valid_ether_addr(mac_addr)) 490 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 491 492 rv = usb_eth_initialize(bis); 493 if (rv < 0) 494 printf("Error %d registering USB_ETHER\n", rv); 495 else 496 n += rv; 497 #endif 498 return n; 499 } 500 #endif 501