1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <errno.h> 13 #include <spl.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/hardware.h> 16 #include <asm/arch/omap.h> 17 #include <asm/arch/ddr_defs.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc_host_def.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/arch/mem.h> 23 #include <asm/io.h> 24 #include <asm/emif.h> 25 #include <asm/gpio.h> 26 #include <i2c.h> 27 #include <miiphy.h> 28 #include <cpsw.h> 29 #include "board.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 34 35 /* MII mode defines */ 36 #define MII_MODE_ENABLE 0x0 37 #define RGMII_MODE_ENABLE 0x3A 38 39 /* GPIO that controls power to DDR on EVM-SK */ 40 #define GPIO_DDR_VTT_EN 7 41 42 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 43 44 /* 45 * Read header information from EEPROM into global structure. 46 */ 47 static int read_eeprom(struct am335x_baseboard_id *header) 48 { 49 /* Check if baseboard eeprom is available */ 50 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 51 puts("Could not probe the EEPROM; something fundamentally " 52 "wrong on the I2C bus.\n"); 53 return -ENODEV; 54 } 55 56 /* read the eeprom using i2c */ 57 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 58 sizeof(struct am335x_baseboard_id))) { 59 puts("Could not read the EEPROM; something fundamentally" 60 " wrong on the I2C bus.\n"); 61 return -EIO; 62 } 63 64 if (header->magic != 0xEE3355AA) { 65 /* 66 * read the eeprom using i2c again, 67 * but use only a 1 byte address 68 */ 69 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 70 sizeof(struct am335x_baseboard_id))) { 71 puts("Could not read the EEPROM; something " 72 "fundamentally wrong on the I2C bus.\n"); 73 return -EIO; 74 } 75 76 if (header->magic != 0xEE3355AA) { 77 printf("Incorrect magic number (0x%x) in EEPROM\n", 78 header->magic); 79 return -EINVAL; 80 } 81 } 82 83 return 0; 84 } 85 86 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 87 static const struct ddr_data ddr2_data = { 88 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 89 (MT47H128M16RT25E_RD_DQS<<20) | 90 (MT47H128M16RT25E_RD_DQS<<10) | 91 (MT47H128M16RT25E_RD_DQS<<0)), 92 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 93 (MT47H128M16RT25E_WR_DQS<<20) | 94 (MT47H128M16RT25E_WR_DQS<<10) | 95 (MT47H128M16RT25E_WR_DQS<<0)), 96 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 97 (MT47H128M16RT25E_PHY_WRLVL<<20) | 98 (MT47H128M16RT25E_PHY_WRLVL<<10) | 99 (MT47H128M16RT25E_PHY_WRLVL<<0)), 100 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 101 (MT47H128M16RT25E_PHY_GATELVL<<20) | 102 (MT47H128M16RT25E_PHY_GATELVL<<10) | 103 (MT47H128M16RT25E_PHY_GATELVL<<0)), 104 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 105 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 106 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 107 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 108 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 109 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 110 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 111 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 112 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 113 .datadldiff0 = PHY_DLL_LOCK_DIFF, 114 }; 115 116 static const struct cmd_control ddr2_cmd_ctrl_data = { 117 .cmd0csratio = MT47H128M16RT25E_RATIO, 118 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 119 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 120 121 .cmd1csratio = MT47H128M16RT25E_RATIO, 122 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 123 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 124 125 .cmd2csratio = MT47H128M16RT25E_RATIO, 126 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 127 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 128 }; 129 130 static const struct emif_regs ddr2_emif_reg_data = { 131 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 132 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 133 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 134 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 135 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 136 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 137 }; 138 139 static const struct ddr_data ddr3_data = { 140 .datardsratio0 = MT41J128MJT125_RD_DQS, 141 .datawdsratio0 = MT41J128MJT125_WR_DQS, 142 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 143 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 144 .datadldiff0 = PHY_DLL_LOCK_DIFF, 145 }; 146 147 static const struct ddr_data ddr3_beagleblack_data = { 148 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 149 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 150 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 151 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 152 .datadldiff0 = PHY_DLL_LOCK_DIFF, 153 }; 154 155 static const struct ddr_data ddr3_evm_data = { 156 .datardsratio0 = MT41J512M8RH125_RD_DQS, 157 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 158 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 159 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 160 .datadldiff0 = PHY_DLL_LOCK_DIFF, 161 }; 162 163 static const struct cmd_control ddr3_cmd_ctrl_data = { 164 .cmd0csratio = MT41J128MJT125_RATIO, 165 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 166 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 167 168 .cmd1csratio = MT41J128MJT125_RATIO, 169 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 170 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 171 172 .cmd2csratio = MT41J128MJT125_RATIO, 173 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 174 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 175 }; 176 177 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 178 .cmd0csratio = MT41K256M16HA125E_RATIO, 179 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 180 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 181 182 .cmd1csratio = MT41K256M16HA125E_RATIO, 183 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 184 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 185 186 .cmd2csratio = MT41K256M16HA125E_RATIO, 187 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 188 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 189 }; 190 191 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 192 .cmd0csratio = MT41J512M8RH125_RATIO, 193 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 194 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 195 196 .cmd1csratio = MT41J512M8RH125_RATIO, 197 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 198 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 199 200 .cmd2csratio = MT41J512M8RH125_RATIO, 201 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 202 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 203 }; 204 205 static struct emif_regs ddr3_emif_reg_data = { 206 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 207 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 208 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 209 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 210 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 211 .zq_config = MT41J128MJT125_ZQ_CFG, 212 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 213 PHY_EN_DYN_PWRDN, 214 }; 215 216 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 217 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 218 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 219 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 220 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 221 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 222 .zq_config = MT41K256M16HA125E_ZQ_CFG, 223 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 224 }; 225 226 static struct emif_regs ddr3_evm_emif_reg_data = { 227 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 228 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 229 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 230 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 231 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 232 .zq_config = MT41J512M8RH125_ZQ_CFG, 233 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 234 PHY_EN_DYN_PWRDN, 235 }; 236 237 #ifdef CONFIG_SPL_OS_BOOT 238 int spl_start_uboot(void) 239 { 240 /* break into full u-boot on 'c' */ 241 return (serial_tstc() && serial_getc() == 'c'); 242 } 243 #endif 244 245 #endif 246 247 /* 248 * early system init of muxing and clocks. 249 */ 250 void s_init(void) 251 { 252 __maybe_unused struct am335x_baseboard_id header; 253 254 /* 255 * The ROM will only have set up sufficient pinmux to allow for the 256 * first 4KiB NOR to be read, we must finish doing what we know of 257 * the NOR mux in this space in order to continue. 258 */ 259 #ifdef CONFIG_NOR_BOOT 260 asm("stmfd sp!, {r2 - r4}"); 261 asm("movw r4, #0x8A4"); 262 asm("movw r3, #0x44E1"); 263 asm("orr r4, r4, r3, lsl #16"); 264 asm("mov r2, #9"); 265 asm("mov r3, #8"); 266 asm("gpmc_mux: str r2, [r4], #4"); 267 asm("subs r3, r3, #1"); 268 asm("bne gpmc_mux"); 269 asm("ldmfd sp!, {r2 - r4}"); 270 #endif 271 272 #ifdef CONFIG_SPL_BUILD 273 /* 274 * Save the boot parameters passed from romcode. 275 * We cannot delay the saving further than this, 276 * to prevent overwrites. 277 */ 278 save_omap_boot_params(); 279 #endif 280 281 /* WDT1 is already running when the bootloader gets control 282 * Disable it to avoid "random" resets 283 */ 284 writel(0xAAAA, &wdtimer->wdtwspr); 285 while (readl(&wdtimer->wdtwwps) != 0x0) 286 ; 287 writel(0x5555, &wdtimer->wdtwspr); 288 while (readl(&wdtimer->wdtwwps) != 0x0) 289 ; 290 291 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 292 /* Setup the PLLs and the clocks for the peripherals */ 293 pll_init(); 294 295 /* Enable RTC32K clock */ 296 rtc32k_enable(); 297 298 #ifdef CONFIG_SERIAL1 299 enable_uart0_pin_mux(); 300 #endif /* CONFIG_SERIAL1 */ 301 #ifdef CONFIG_SERIAL2 302 enable_uart1_pin_mux(); 303 #endif /* CONFIG_SERIAL2 */ 304 #ifdef CONFIG_SERIAL3 305 enable_uart2_pin_mux(); 306 #endif /* CONFIG_SERIAL3 */ 307 #ifdef CONFIG_SERIAL4 308 enable_uart3_pin_mux(); 309 #endif /* CONFIG_SERIAL4 */ 310 #ifdef CONFIG_SERIAL5 311 enable_uart4_pin_mux(); 312 #endif /* CONFIG_SERIAL5 */ 313 #ifdef CONFIG_SERIAL6 314 enable_uart5_pin_mux(); 315 #endif /* CONFIG_SERIAL6 */ 316 317 uart_soft_reset(); 318 319 #if defined(CONFIG_NOR_BOOT) 320 /* We want our console now. */ 321 gd->baudrate = CONFIG_BAUDRATE; 322 serial_init(); 323 gd->have_console = 1; 324 #else 325 gd = &gdata; 326 327 preloader_console_init(); 328 #endif 329 330 /* Initalize the board header */ 331 enable_i2c0_pin_mux(); 332 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 333 if (read_eeprom(&header) < 0) 334 puts("Could not get board ID.\n"); 335 336 enable_board_pin_mux(&header); 337 if (board_is_evm_sk(&header)) { 338 /* 339 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 340 * This is safe enough to do on older revs. 341 */ 342 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 343 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 344 } 345 346 if (board_is_evm_sk(&header)) 347 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 348 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 349 else if (board_is_bone_lt(&header)) 350 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 351 &ddr3_beagleblack_data, 352 &ddr3_beagleblack_cmd_ctrl_data, 353 &ddr3_beagleblack_emif_reg_data, 0); 354 else if (board_is_evm_15_or_later(&header)) 355 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 356 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 357 else 358 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 359 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 360 #endif 361 } 362 363 /* 364 * Basic board specific setup. Pinmux has been handled already. 365 */ 366 int board_init(void) 367 { 368 #ifdef CONFIG_NOR 369 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, 370 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, 371 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; 372 #endif 373 374 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 375 376 gpmc_init(); 377 378 #ifdef CONFIG_NOR 379 /* Reconfigure CS0 for NOR instead of NAND. */ 380 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], 381 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); 382 #endif 383 384 return 0; 385 } 386 387 #ifdef CONFIG_BOARD_LATE_INIT 388 int board_late_init(void) 389 { 390 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 391 char safe_string[HDR_NAME_LEN + 1]; 392 struct am335x_baseboard_id header; 393 394 if (read_eeprom(&header) < 0) 395 puts("Could not get board ID.\n"); 396 397 /* Now set variables based on the header. */ 398 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 399 safe_string[sizeof(header.name)] = 0; 400 setenv("board_name", safe_string); 401 402 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 403 safe_string[sizeof(header.version)] = 0; 404 setenv("board_rev", safe_string); 405 #endif 406 407 return 0; 408 } 409 #endif 410 411 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 412 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 413 static void cpsw_control(int enabled) 414 { 415 /* VTP can be added here */ 416 417 return; 418 } 419 420 static struct cpsw_slave_data cpsw_slaves[] = { 421 { 422 .slave_reg_ofs = 0x208, 423 .sliver_reg_ofs = 0xd80, 424 .phy_id = 0, 425 }, 426 { 427 .slave_reg_ofs = 0x308, 428 .sliver_reg_ofs = 0xdc0, 429 .phy_id = 1, 430 }, 431 }; 432 433 static struct cpsw_platform_data cpsw_data = { 434 .mdio_base = CPSW_MDIO_BASE, 435 .cpsw_base = CPSW_BASE, 436 .mdio_div = 0xff, 437 .channels = 8, 438 .cpdma_reg_ofs = 0x800, 439 .slaves = 1, 440 .slave_data = cpsw_slaves, 441 .ale_reg_ofs = 0xd00, 442 .ale_entries = 1024, 443 .host_port_reg_ofs = 0x108, 444 .hw_stats_reg_ofs = 0x900, 445 .bd_ram_ofs = 0x2000, 446 .mac_control = (1 << 5), 447 .control = cpsw_control, 448 .host_port_num = 0, 449 .version = CPSW_CTRL_VERSION_2, 450 }; 451 #endif 452 453 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 454 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 455 int board_eth_init(bd_t *bis) 456 { 457 int rv, n = 0; 458 uint8_t mac_addr[6]; 459 uint32_t mac_hi, mac_lo; 460 __maybe_unused struct am335x_baseboard_id header; 461 462 /* try reading mac address from efuse */ 463 mac_lo = readl(&cdev->macid0l); 464 mac_hi = readl(&cdev->macid0h); 465 mac_addr[0] = mac_hi & 0xFF; 466 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 467 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 468 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 469 mac_addr[4] = mac_lo & 0xFF; 470 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 471 472 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 473 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 474 if (!getenv("ethaddr")) { 475 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 476 477 if (is_valid_ether_addr(mac_addr)) 478 eth_setenv_enetaddr("ethaddr", mac_addr); 479 } 480 481 #ifdef CONFIG_DRIVER_TI_CPSW 482 if (read_eeprom(&header) < 0) 483 puts("Could not get board ID.\n"); 484 485 if (board_is_bone(&header) || board_is_bone_lt(&header) || 486 board_is_idk(&header)) { 487 writel(MII_MODE_ENABLE, &cdev->miisel); 488 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 489 PHY_INTERFACE_MODE_MII; 490 } else { 491 writel(RGMII_MODE_ENABLE, &cdev->miisel); 492 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 493 PHY_INTERFACE_MODE_RGMII; 494 } 495 496 rv = cpsw_register(&cpsw_data); 497 if (rv < 0) 498 printf("Error %d registering CPSW switch\n", rv); 499 else 500 n += rv; 501 #endif 502 503 /* 504 * 505 * CPSW RGMII Internal Delay Mode is not supported in all PVT 506 * operating points. So we must set the TX clock delay feature 507 * in the AR8051 PHY. Since we only support a single ethernet 508 * device in U-Boot, we only do this for the first instance. 509 */ 510 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 511 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 512 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 513 #define AR8051_RGMII_TX_CLK_DLY 0x100 514 515 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 516 const char *devname; 517 devname = miiphy_get_current_dev(); 518 519 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 520 AR8051_DEBUG_RGMII_CLK_DLY_REG); 521 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 522 AR8051_RGMII_TX_CLK_DLY); 523 } 524 #endif 525 #if defined(CONFIG_USB_ETHER) && \ 526 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 527 if (is_valid_ether_addr(mac_addr)) 528 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 529 530 rv = usb_eth_initialize(bis); 531 if (rv < 0) 532 printf("Error %d registering USB_ETHER\n", rv); 533 else 534 n += rv; 535 #endif 536 return n; 537 } 538 #endif 539