1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <common.h> 20 #include <errno.h> 21 #include <spl.h> 22 #include <asm/arch/cpu.h> 23 #include <asm/arch/hardware.h> 24 #include <asm/arch/omap.h> 25 #include <asm/arch/ddr_defs.h> 26 #include <asm/arch/clock.h> 27 #include <asm/arch/gpio.h> 28 #include <asm/arch/mmc_host_def.h> 29 #include <asm/arch/sys_proto.h> 30 #include <asm/io.h> 31 #include <asm/emif.h> 32 #include <asm/gpio.h> 33 #include <i2c.h> 34 #include <miiphy.h> 35 #include <cpsw.h> 36 #include "board.h" 37 38 DECLARE_GLOBAL_DATA_PTR; 39 40 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; 41 #ifdef CONFIG_SPL_BUILD 42 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; 43 #endif 44 45 /* MII mode defines */ 46 #define MII_MODE_ENABLE 0x0 47 #define RGMII_MODE_ENABLE 0x3A 48 49 /* GPIO that controls power to DDR on EVM-SK */ 50 #define GPIO_DDR_VTT_EN 7 51 52 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 53 54 static struct am335x_baseboard_id __attribute__((section (".data"))) header; 55 56 static inline int board_is_bone(void) 57 { 58 return !strncmp(header.name, "A335BONE", HDR_NAME_LEN); 59 } 60 61 static inline int board_is_bone_lt(void) 62 { 63 return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN); 64 } 65 66 static inline int board_is_evm_sk(void) 67 { 68 return !strncmp("A335X_SK", header.name, HDR_NAME_LEN); 69 } 70 71 static inline int board_is_idk(void) 72 { 73 return !strncmp(header.config, "SKU#02", 6); 74 } 75 76 int board_is_evm_15_or_later(void) 77 { 78 return (!strncmp("A33515BB", header.name, 8) && 79 strncmp("1.5", header.version, 3) <= 0); 80 } 81 82 /* 83 * Read header information from EEPROM into global structure. 84 */ 85 static int read_eeprom(void) 86 { 87 /* Check if baseboard eeprom is available */ 88 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 89 puts("Could not probe the EEPROM; something fundamentally " 90 "wrong on the I2C bus.\n"); 91 return -ENODEV; 92 } 93 94 /* read the eeprom using i2c */ 95 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, 96 sizeof(header))) { 97 puts("Could not read the EEPROM; something fundamentally" 98 " wrong on the I2C bus.\n"); 99 return -EIO; 100 } 101 102 if (header.magic != 0xEE3355AA) { 103 /* 104 * read the eeprom using i2c again, 105 * but use only a 1 byte address 106 */ 107 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, 108 (uchar *)&header, sizeof(header))) { 109 puts("Could not read the EEPROM; something " 110 "fundamentally wrong on the I2C bus.\n"); 111 return -EIO; 112 } 113 114 if (header.magic != 0xEE3355AA) { 115 printf("Incorrect magic number (0x%x) in EEPROM\n", 116 header.magic); 117 return -EINVAL; 118 } 119 } 120 121 return 0; 122 } 123 124 /* UART Defines */ 125 #ifdef CONFIG_SPL_BUILD 126 #define UART_RESET (0x1 << 1) 127 #define UART_CLK_RUNNING_MASK 0x1 128 #define UART_SMART_IDLE_EN (0x1 << 0x3) 129 130 static void rtc32k_enable(void) 131 { 132 struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; 133 134 /* 135 * Unlock the RTC's registers. For more details please see the 136 * RTC_SS section of the TRM. In order to unlock we need to 137 * write these specific values (keys) in this order. 138 */ 139 writel(0x83e70b13, &rtc->kick0r); 140 writel(0x95a4f1e0, &rtc->kick1r); 141 142 /* Enable the RTC 32K OSC by setting bits 3 and 6. */ 143 writel((1 << 3) | (1 << 6), &rtc->osc); 144 } 145 146 static const struct ddr_data ddr2_data = { 147 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 148 (MT47H128M16RT25E_RD_DQS<<20) | 149 (MT47H128M16RT25E_RD_DQS<<10) | 150 (MT47H128M16RT25E_RD_DQS<<0)), 151 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 152 (MT47H128M16RT25E_WR_DQS<<20) | 153 (MT47H128M16RT25E_WR_DQS<<10) | 154 (MT47H128M16RT25E_WR_DQS<<0)), 155 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 156 (MT47H128M16RT25E_PHY_WRLVL<<20) | 157 (MT47H128M16RT25E_PHY_WRLVL<<10) | 158 (MT47H128M16RT25E_PHY_WRLVL<<0)), 159 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 160 (MT47H128M16RT25E_PHY_GATELVL<<20) | 161 (MT47H128M16RT25E_PHY_GATELVL<<10) | 162 (MT47H128M16RT25E_PHY_GATELVL<<0)), 163 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 164 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 165 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 166 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 167 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 168 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 169 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 170 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 171 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 172 .datadldiff0 = PHY_DLL_LOCK_DIFF, 173 }; 174 175 static const struct cmd_control ddr2_cmd_ctrl_data = { 176 .cmd0csratio = MT47H128M16RT25E_RATIO, 177 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 178 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 179 180 .cmd1csratio = MT47H128M16RT25E_RATIO, 181 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 182 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 183 184 .cmd2csratio = MT47H128M16RT25E_RATIO, 185 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 186 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 187 }; 188 189 static const struct emif_regs ddr2_emif_reg_data = { 190 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 191 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 192 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 193 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 194 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 195 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 196 }; 197 198 static const struct ddr_data ddr3_data = { 199 .datardsratio0 = MT41J128MJT125_RD_DQS, 200 .datawdsratio0 = MT41J128MJT125_WR_DQS, 201 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 202 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 203 .datadldiff0 = PHY_DLL_LOCK_DIFF, 204 }; 205 206 static const struct ddr_data ddr3_evm_data = { 207 .datardsratio0 = MT41J512M8RH125_RD_DQS, 208 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 209 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 210 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 211 .datadldiff0 = PHY_DLL_LOCK_DIFF, 212 }; 213 214 static const struct cmd_control ddr3_cmd_ctrl_data = { 215 .cmd0csratio = MT41J128MJT125_RATIO, 216 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 217 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 218 219 .cmd1csratio = MT41J128MJT125_RATIO, 220 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 221 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 222 223 .cmd2csratio = MT41J128MJT125_RATIO, 224 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 225 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 226 }; 227 228 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 229 .cmd0csratio = MT41J512M8RH125_RATIO, 230 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 231 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 232 233 .cmd1csratio = MT41J512M8RH125_RATIO, 234 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 235 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 236 237 .cmd2csratio = MT41J512M8RH125_RATIO, 238 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 239 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 240 }; 241 242 static struct emif_regs ddr3_emif_reg_data = { 243 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 244 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 245 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 246 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 247 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 248 .zq_config = MT41J128MJT125_ZQ_CFG, 249 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, 250 }; 251 252 static struct emif_regs ddr3_evm_emif_reg_data = { 253 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 254 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 255 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 256 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 257 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 258 .zq_config = MT41J512M8RH125_ZQ_CFG, 259 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY, 260 }; 261 #endif 262 263 /* 264 * early system init of muxing and clocks. 265 */ 266 void s_init(void) 267 { 268 /* WDT1 is already running when the bootloader gets control 269 * Disable it to avoid "random" resets 270 */ 271 writel(0xAAAA, &wdtimer->wdtwspr); 272 while (readl(&wdtimer->wdtwwps) != 0x0) 273 ; 274 writel(0x5555, &wdtimer->wdtwspr); 275 while (readl(&wdtimer->wdtwwps) != 0x0) 276 ; 277 278 #ifdef CONFIG_SPL_BUILD 279 /* Setup the PLLs and the clocks for the peripherals */ 280 pll_init(); 281 282 /* Enable RTC32K clock */ 283 rtc32k_enable(); 284 285 /* UART softreset */ 286 u32 regVal; 287 288 #ifdef CONFIG_SERIAL1 289 enable_uart0_pin_mux(); 290 #endif /* CONFIG_SERIAL1 */ 291 #ifdef CONFIG_SERIAL2 292 enable_uart1_pin_mux(); 293 #endif /* CONFIG_SERIAL2 */ 294 #ifdef CONFIG_SERIAL3 295 enable_uart2_pin_mux(); 296 #endif /* CONFIG_SERIAL3 */ 297 #ifdef CONFIG_SERIAL4 298 enable_uart3_pin_mux(); 299 #endif /* CONFIG_SERIAL4 */ 300 #ifdef CONFIG_SERIAL5 301 enable_uart4_pin_mux(); 302 #endif /* CONFIG_SERIAL5 */ 303 #ifdef CONFIG_SERIAL6 304 enable_uart5_pin_mux(); 305 #endif /* CONFIG_SERIAL6 */ 306 307 regVal = readl(&uart_base->uartsyscfg); 308 regVal |= UART_RESET; 309 writel(regVal, &uart_base->uartsyscfg); 310 while ((readl(&uart_base->uartsyssts) & 311 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) 312 ; 313 314 /* Disable smart idle */ 315 regVal = readl(&uart_base->uartsyscfg); 316 regVal |= UART_SMART_IDLE_EN; 317 writel(regVal, &uart_base->uartsyscfg); 318 319 gd = &gdata; 320 321 preloader_console_init(); 322 323 /* Initalize the board header */ 324 enable_i2c0_pin_mux(); 325 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 326 if (read_eeprom() < 0) 327 puts("Could not get board ID.\n"); 328 329 enable_board_pin_mux(&header); 330 if (board_is_evm_sk()) { 331 /* 332 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 333 * This is safe enough to do on older revs. 334 */ 335 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 336 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 337 } 338 339 if (board_is_evm_sk() || board_is_bone_lt()) 340 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 341 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); 342 else if (board_is_evm_15_or_later()) 343 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 344 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data); 345 else 346 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 347 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); 348 #endif 349 } 350 351 /* 352 * Basic board specific setup. Pinmux has been handled already. 353 */ 354 int board_init(void) 355 { 356 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 357 if (read_eeprom() < 0) 358 puts("Could not get board ID.\n"); 359 360 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; 361 362 gpmc_init(); 363 364 return 0; 365 } 366 367 #ifdef CONFIG_BOARD_LATE_INIT 368 int board_late_init(void) 369 { 370 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 371 char safe_string[HDR_NAME_LEN + 1]; 372 373 /* Now set variables based on the header. */ 374 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 375 safe_string[sizeof(header.name)] = 0; 376 setenv("board_name", safe_string); 377 378 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 379 safe_string[sizeof(header.version)] = 0; 380 setenv("board_rev", safe_string); 381 #endif 382 383 return 0; 384 } 385 #endif 386 387 #ifdef CONFIG_DRIVER_TI_CPSW 388 static void cpsw_control(int enabled) 389 { 390 /* VTP can be added here */ 391 392 return; 393 } 394 395 static struct cpsw_slave_data cpsw_slaves[] = { 396 { 397 .slave_reg_ofs = 0x208, 398 .sliver_reg_ofs = 0xd80, 399 .phy_id = 0, 400 }, 401 { 402 .slave_reg_ofs = 0x308, 403 .sliver_reg_ofs = 0xdc0, 404 .phy_id = 1, 405 }, 406 }; 407 408 static struct cpsw_platform_data cpsw_data = { 409 .mdio_base = AM335X_CPSW_MDIO_BASE, 410 .cpsw_base = AM335X_CPSW_BASE, 411 .mdio_div = 0xff, 412 .channels = 8, 413 .cpdma_reg_ofs = 0x800, 414 .slaves = 1, 415 .slave_data = cpsw_slaves, 416 .ale_reg_ofs = 0xd00, 417 .ale_entries = 1024, 418 .host_port_reg_ofs = 0x108, 419 .hw_stats_reg_ofs = 0x900, 420 .mac_control = (1 << 5), 421 .control = cpsw_control, 422 .host_port_num = 0, 423 .version = CPSW_CTRL_VERSION_2, 424 }; 425 #endif 426 427 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 428 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 429 int board_eth_init(bd_t *bis) 430 { 431 int rv, n = 0; 432 #ifdef CONFIG_DRIVER_TI_CPSW 433 uint8_t mac_addr[6]; 434 uint32_t mac_hi, mac_lo; 435 436 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) { 437 printf("<ethaddr> not set. Reading from E-fuse\n"); 438 /* try reading mac address from efuse */ 439 mac_lo = readl(&cdev->macid0l); 440 mac_hi = readl(&cdev->macid0h); 441 mac_addr[0] = mac_hi & 0xFF; 442 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 443 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 444 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 445 mac_addr[4] = mac_lo & 0xFF; 446 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 447 448 if (is_valid_ether_addr(mac_addr)) 449 eth_setenv_enetaddr("ethaddr", mac_addr); 450 else 451 goto try_usbether; 452 } 453 454 if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { 455 writel(MII_MODE_ENABLE, &cdev->miisel); 456 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 457 PHY_INTERFACE_MODE_MII; 458 } else { 459 writel(RGMII_MODE_ENABLE, &cdev->miisel); 460 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 461 PHY_INTERFACE_MODE_RGMII; 462 } 463 464 rv = cpsw_register(&cpsw_data); 465 if (rv < 0) 466 printf("Error %d registering CPSW switch\n", rv); 467 else 468 n += rv; 469 #endif 470 try_usbether: 471 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) 472 rv = usb_eth_initialize(bis); 473 if (rv < 0) 474 printf("Error %d registering USB_ETHER\n", rv); 475 else 476 n += rv; 477 #endif 478 return n; 479 } 480 #endif 481