1*aea02abeSStefan Roese /* 2*aea02abeSStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*aea02abeSStefan Roese * 4*aea02abeSStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*aea02abeSStefan Roese */ 6*aea02abeSStefan Roese 7*aea02abeSStefan Roese /* Base addresses for the SPI direct access mode */ 8*aea02abeSStefan Roese #define SPI_BUS0_DEV1_BASE 0xe0000000 9*aea02abeSStefan Roese #define SPI_BUS0_DEV1_SIZE (1 << 20) 10*aea02abeSStefan Roese #define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE) 11*aea02abeSStefan Roese 12*aea02abeSStefan Roese void board_fpga_add(void); 13