1*aea02abeSStefan Roese /*
2*aea02abeSStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*aea02abeSStefan Roese *
4*aea02abeSStefan Roese * SPDX-License-Identifier: GPL-2.0+
5*aea02abeSStefan Roese */
6*aea02abeSStefan Roese
7*aea02abeSStefan Roese #include <common.h>
8*aea02abeSStefan Roese #include <altera.h>
9*aea02abeSStefan Roese #include <errno.h>
10*aea02abeSStefan Roese #include <asm/gpio.h>
11*aea02abeSStefan Roese #include <asm/io.h>
12*aea02abeSStefan Roese #include <asm/arch/cpu.h>
13*aea02abeSStefan Roese #include <asm/arch/soc.h>
14*aea02abeSStefan Roese #include <asm/arch-mvebu/spi.h>
15*aea02abeSStefan Roese #include "theadorable.h"
16*aea02abeSStefan Roese
17*aea02abeSStefan Roese /*
18*aea02abeSStefan Roese * FPGA programming support
19*aea02abeSStefan Roese */
fpga_pre_fn(int cookie)20*aea02abeSStefan Roese static int fpga_pre_fn(int cookie)
21*aea02abeSStefan Roese {
22*aea02abeSStefan Roese int gpio_config = COOKIE2CONFIG(cookie);
23*aea02abeSStefan Roese int gpio_done = COOKIE2DONE(cookie);
24*aea02abeSStefan Roese int ret;
25*aea02abeSStefan Roese
26*aea02abeSStefan Roese debug("%s (%d): cookie=%08x gpio_config=%d gpio_done=%d\n",
27*aea02abeSStefan Roese __func__, __LINE__, cookie, gpio_config, gpio_done);
28*aea02abeSStefan Roese
29*aea02abeSStefan Roese /* Configure config pin */
30*aea02abeSStefan Roese /* Set to output */
31*aea02abeSStefan Roese ret = gpio_request(gpio_config, "CONFIG");
32*aea02abeSStefan Roese if (ret < 0)
33*aea02abeSStefan Roese return ret;
34*aea02abeSStefan Roese gpio_direction_output(gpio_config, 1);
35*aea02abeSStefan Roese
36*aea02abeSStefan Roese /* Configure done pin */
37*aea02abeSStefan Roese /* Set to input */
38*aea02abeSStefan Roese ret = gpio_request(gpio_done, "DONE");
39*aea02abeSStefan Roese if (ret < 0)
40*aea02abeSStefan Roese return ret;
41*aea02abeSStefan Roese
42*aea02abeSStefan Roese gpio_direction_input(gpio_done);
43*aea02abeSStefan Roese
44*aea02abeSStefan Roese return 0;
45*aea02abeSStefan Roese }
46*aea02abeSStefan Roese
fpga_config_fn(int assert,int flush,int cookie)47*aea02abeSStefan Roese static int fpga_config_fn(int assert, int flush, int cookie)
48*aea02abeSStefan Roese {
49*aea02abeSStefan Roese int gpio_config = COOKIE2CONFIG(cookie);
50*aea02abeSStefan Roese
51*aea02abeSStefan Roese debug("%s (%d): cookie=%08x gpio_config=%d\n",
52*aea02abeSStefan Roese __func__, __LINE__, cookie, gpio_config);
53*aea02abeSStefan Roese
54*aea02abeSStefan Roese if (assert)
55*aea02abeSStefan Roese gpio_set_value(gpio_config, 1);
56*aea02abeSStefan Roese else
57*aea02abeSStefan Roese gpio_set_value(gpio_config, 0);
58*aea02abeSStefan Roese
59*aea02abeSStefan Roese return 0;
60*aea02abeSStefan Roese }
61*aea02abeSStefan Roese
fpga_write_fn(const void * buf,size_t len,int flush,int cookie)62*aea02abeSStefan Roese static int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
63*aea02abeSStefan Roese {
64*aea02abeSStefan Roese int spi_bus = COOKIE2SPI_BUS(cookie);
65*aea02abeSStefan Roese int spi_dev = COOKIE2SPI_DEV(cookie);
66*aea02abeSStefan Roese struct kwspi_registers *reg;
67*aea02abeSStefan Roese u32 control_reg;
68*aea02abeSStefan Roese u32 config_reg;
69*aea02abeSStefan Roese void *dst;
70*aea02abeSStefan Roese
71*aea02abeSStefan Roese /*
72*aea02abeSStefan Roese * Write data to FPGA attached to SPI bus via SPI direct write.
73*aea02abeSStefan Roese * This results in the fastest and easiest way to program the
74*aea02abeSStefan Roese * bitstream into the FPGA.
75*aea02abeSStefan Roese */
76*aea02abeSStefan Roese debug("%s (%d): cookie=%08x spi_bus=%d spi_dev=%d\n",
77*aea02abeSStefan Roese __func__, __LINE__, cookie, spi_bus, spi_dev);
78*aea02abeSStefan Roese
79*aea02abeSStefan Roese if (spi_bus == 0) {
80*aea02abeSStefan Roese reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10600);
81*aea02abeSStefan Roese dst = (void *)SPI_BUS0_DEV1_BASE;
82*aea02abeSStefan Roese } else {
83*aea02abeSStefan Roese reg = (struct kwspi_registers *)MVEBU_REGISTER(0x10680);
84*aea02abeSStefan Roese dst = (void *)SPI_BUS1_DEV2_BASE;
85*aea02abeSStefan Roese }
86*aea02abeSStefan Roese
87*aea02abeSStefan Roese /* Configure SPI controller for direct access mode */
88*aea02abeSStefan Roese control_reg = readl(®->ctrl);
89*aea02abeSStefan Roese config_reg = readl(®->cfg);
90*aea02abeSStefan Roese writel(0x00000214, ®->cfg); /* 27MHz clock */
91*aea02abeSStefan Roese writel(0x00000000, ®->dw_cfg); /* don't de-asset CS */
92*aea02abeSStefan Roese writel(KWSPI_CSN_ACT, ®->ctrl); /* activate CS */
93*aea02abeSStefan Roese
94*aea02abeSStefan Roese /* Copy data to the SPI direct mapped window */
95*aea02abeSStefan Roese memcpy(dst, buf, len);
96*aea02abeSStefan Roese
97*aea02abeSStefan Roese /* Restore original register values */
98*aea02abeSStefan Roese writel(control_reg, ®->ctrl);
99*aea02abeSStefan Roese writel(config_reg, ®->cfg);
100*aea02abeSStefan Roese
101*aea02abeSStefan Roese return 0;
102*aea02abeSStefan Roese }
103*aea02abeSStefan Roese
104*aea02abeSStefan Roese /* Returns the state of CONF_DONE Pin */
fpga_done_fn(int cookie)105*aea02abeSStefan Roese static int fpga_done_fn(int cookie)
106*aea02abeSStefan Roese {
107*aea02abeSStefan Roese int gpio_done = COOKIE2DONE(cookie);
108*aea02abeSStefan Roese unsigned long ts;
109*aea02abeSStefan Roese
110*aea02abeSStefan Roese debug("%s (%d): cookie=%08x gpio_done=%d\n",
111*aea02abeSStefan Roese __func__, __LINE__, cookie, gpio_done);
112*aea02abeSStefan Roese
113*aea02abeSStefan Roese ts = get_timer(0);
114*aea02abeSStefan Roese do {
115*aea02abeSStefan Roese if (gpio_get_value(gpio_done))
116*aea02abeSStefan Roese return 0;
117*aea02abeSStefan Roese } while (get_timer(ts) < 1000);
118*aea02abeSStefan Roese
119*aea02abeSStefan Roese /* timeout so return error */
120*aea02abeSStefan Roese return -ENODEV;
121*aea02abeSStefan Roese }
122*aea02abeSStefan Roese
123*aea02abeSStefan Roese static altera_board_specific_func stratixv_fns = {
124*aea02abeSStefan Roese .pre = fpga_pre_fn,
125*aea02abeSStefan Roese .config = fpga_config_fn,
126*aea02abeSStefan Roese .write = fpga_write_fn,
127*aea02abeSStefan Roese .done = fpga_done_fn,
128*aea02abeSStefan Roese };
129*aea02abeSStefan Roese
130*aea02abeSStefan Roese static Altera_desc altera_fpga[] = {
131*aea02abeSStefan Roese {
132*aea02abeSStefan Roese /* Family */
133*aea02abeSStefan Roese Altera_StratixV,
134*aea02abeSStefan Roese /* Interface type */
135*aea02abeSStefan Roese passive_serial,
136*aea02abeSStefan Roese /* No limitation as additional data will be ignored */
137*aea02abeSStefan Roese -1,
138*aea02abeSStefan Roese /* Device function table */
139*aea02abeSStefan Roese (void *)&stratixv_fns,
140*aea02abeSStefan Roese /* Base interface address specified in driver */
141*aea02abeSStefan Roese NULL,
142*aea02abeSStefan Roese /* Cookie implementation */
143*aea02abeSStefan Roese /*
144*aea02abeSStefan Roese * In this 32bit word the following information is coded:
145*aea02abeSStefan Roese * Bit 31 ... Bit 0
146*aea02abeSStefan Roese * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
147*aea02abeSStefan Roese */
148*aea02abeSStefan Roese FPGA_COOKIE(0, 1, 26, 7)
149*aea02abeSStefan Roese },
150*aea02abeSStefan Roese {
151*aea02abeSStefan Roese /* Family */
152*aea02abeSStefan Roese Altera_StratixV,
153*aea02abeSStefan Roese /* Interface type */
154*aea02abeSStefan Roese passive_serial,
155*aea02abeSStefan Roese /* No limitation as additional data will be ignored */
156*aea02abeSStefan Roese -1,
157*aea02abeSStefan Roese /* Device function table */
158*aea02abeSStefan Roese (void *)&stratixv_fns,
159*aea02abeSStefan Roese /* Base interface address specified in driver */
160*aea02abeSStefan Roese NULL,
161*aea02abeSStefan Roese /* Cookie implementation */
162*aea02abeSStefan Roese /*
163*aea02abeSStefan Roese * In this 32bit word the following information is coded:
164*aea02abeSStefan Roese * Bit 31 ... Bit 0
165*aea02abeSStefan Roese * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
166*aea02abeSStefan Roese */
167*aea02abeSStefan Roese FPGA_COOKIE(1, 2, 29, 9)
168*aea02abeSStefan Roese },
169*aea02abeSStefan Roese };
170*aea02abeSStefan Roese
171*aea02abeSStefan Roese /* Add device descriptor to FPGA device table */
board_fpga_add(void)172*aea02abeSStefan Roese void board_fpga_add(void)
173*aea02abeSStefan Roese {
174*aea02abeSStefan Roese int i;
175*aea02abeSStefan Roese
176*aea02abeSStefan Roese fpga_init();
177*aea02abeSStefan Roese for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
178*aea02abeSStefan Roese fpga_add(fpga_altera, &altera_fpga[i]);
179*aea02abeSStefan Roese }
180