139f0023eSMatthias Weisser/* 239f0023eSMatthias Weisser * (C) Copyright 2011 339f0023eSMatthias Weisser * Matthias Weisser <weisserm@arcor.de> 439f0023eSMatthias Weisser * 539f0023eSMatthias Weisser * (C) Copyright 2009 DENX Software Engineering 639f0023eSMatthias Weisser * Author: John Rigby <jrigby@gmail.com> 739f0023eSMatthias Weisser * 839f0023eSMatthias Weisser * Based on U-Boot and RedBoot sources for several different i.mx 939f0023eSMatthias Weisser * platforms. 1039f0023eSMatthias Weisser * 1139f0023eSMatthias Weisser * This program is free software; you can redistribute it and/or 1239f0023eSMatthias Weisser * modify it under the terms of the GNU General Public License as 1339f0023eSMatthias Weisser * published by the Free Software Foundation; either version 2 of 1439f0023eSMatthias Weisser * the License, or (at your option) any later version. 1539f0023eSMatthias Weisser * 1639f0023eSMatthias Weisser * This program is distributed in the hope that it will be useful, 1739f0023eSMatthias Weisser * but WITHOUT ANY WARRANTY; without even the implied warranty of 1839f0023eSMatthias Weisser * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1939f0023eSMatthias Weisser * GNU General Public License for more details. 2039f0023eSMatthias Weisser * 2139f0023eSMatthias Weisser * You should have received a copy of the GNU General Public License 2239f0023eSMatthias Weisser * along with this program; if not, write to the Free Software 2339f0023eSMatthias Weisser * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 2439f0023eSMatthias Weisser * MA 02111-1307 USA 2539f0023eSMatthias Weisser */ 2639f0023eSMatthias Weisser 2739f0023eSMatthias Weisser#include <asm/macro.h> 2839f0023eSMatthias Weisser#include <asm/arch/macro.h> 2939f0023eSMatthias Weisser#include <asm/arch/imx-regs.h> 30*a4814a69SStefano Babic#include <generated/asm-offsets.h> 3139f0023eSMatthias Weisser 3239f0023eSMatthias Weisser/* 3339f0023eSMatthias Weisser * clocks 3439f0023eSMatthias Weisser */ 3539f0023eSMatthias Weisser.macro init_clocks 3639f0023eSMatthias Weisser 3739f0023eSMatthias Weisser /* disable clock output */ 3839f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 3939f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 4039f0023eSMatthias Weisser 4139f0023eSMatthias Weisser /* 4239f0023eSMatthias Weisser * enable all implemented clocks in all three 4339f0023eSMatthias Weisser * clock control registers 4439f0023eSMatthias Weisser */ 4539f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff 4639f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff 4739f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff 4839f0023eSMatthias Weisser 4939f0023eSMatthias Weisser /* Devide NAND clock by 32 */ 5039f0023eSMatthias Weisser write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F 5139f0023eSMatthias Weisser.endm 5239f0023eSMatthias Weisser 5339f0023eSMatthias Weisser/* 5439f0023eSMatthias Weisser * sdram controller init 5539f0023eSMatthias Weisser */ 5639f0023eSMatthias Weisser.macro init_lpddr 5739f0023eSMatthias Weisser ldr r0, =IMX_ESDRAMC_BASE 5839f0023eSMatthias Weisser ldr r2, =IMX_SDRAM_BANK0_BASE 5939f0023eSMatthias Weisser 6039f0023eSMatthias Weisser /* 6139f0023eSMatthias Weisser * reset SDRAM controller 6239f0023eSMatthias Weisser * then wait for initialization to complete 6339f0023eSMatthias Weisser */ 6439f0023eSMatthias Weisser ldr r1, =(1 << 1) | (1 << 2) 6539f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDMISC] 6639f0023eSMatthias Weisser1: ldr r3, [r0, #ESDRAMC_ESDMISC] 6739f0023eSMatthias Weisser tst r3, #(1 << 31) 6839f0023eSMatthias Weisser beq 1b 6939f0023eSMatthias Weisser ldr r1, =(1 << 2) 7039f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDMISC] 7139f0023eSMatthias Weisser 7239f0023eSMatthias Weisser ldr r1, =0x002a7420 7339f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCFG0] 7439f0023eSMatthias Weisser 7539f0023eSMatthias Weisser /* control | precharge */ 7639f0023eSMatthias Weisser ldr r1, =0x92216008 7739f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 7839f0023eSMatthias Weisser /* dram command encoded in address */ 7939f0023eSMatthias Weisser str r1, [r2, #0x400] 8039f0023eSMatthias Weisser 8139f0023eSMatthias Weisser /* auto refresh */ 8239f0023eSMatthias Weisser ldr r1, =0xa2216008 8339f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 8439f0023eSMatthias Weisser /* read dram twice to auto refresh */ 8539f0023eSMatthias Weisser ldr r3, [r2] 8639f0023eSMatthias Weisser ldr r3, [r2] 8739f0023eSMatthias Weisser 8839f0023eSMatthias Weisser /* control | load mode */ 8939f0023eSMatthias Weisser ldr r1, =0xb2216008 9039f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 9139f0023eSMatthias Weisser 9239f0023eSMatthias Weisser /* mode register of lpddram */ 9339f0023eSMatthias Weisser strb r1, [r2, #0x33] 9439f0023eSMatthias Weisser 9539f0023eSMatthias Weisser /* extended mode register of lpddrram */ 9639f0023eSMatthias Weisser ldr r2, =0x81000000 9739f0023eSMatthias Weisser strb r1, [r2] 9839f0023eSMatthias Weisser 9939f0023eSMatthias Weisser /* control | normal */ 10039f0023eSMatthias Weisser ldr r1, =0x82216008 10139f0023eSMatthias Weisser str r1, [r0, #ESDRAMC_ESDCTL0] 10239f0023eSMatthias Weisser.endm 10339f0023eSMatthias Weisser 10439f0023eSMatthias Weisser.globl lowlevel_init 10539f0023eSMatthias Weisserlowlevel_init: 10639f0023eSMatthias Weisser init_aips 10739f0023eSMatthias Weisser init_max 10839f0023eSMatthias Weisser init_clocks 10939f0023eSMatthias Weisser init_lpddr 11039f0023eSMatthias Weisser mov pc, lr 111