1*a373024eSAngelo Dureghello/* 2*a373024eSAngelo Dureghello * Board-specific early ddr/sdram init. 3*a373024eSAngelo Dureghello * 4*a373024eSAngelo Dureghello * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 5*a373024eSAngelo Dureghello * 6*a373024eSAngelo Dureghello * SPDX-License-Identifier: GPL-2.0+ 7*a373024eSAngelo Dureghello */ 8*a373024eSAngelo Dureghello 9*a373024eSAngelo Dureghello.equ PPMCR0, 0xfc04002d 10*a373024eSAngelo Dureghello.equ MSCR_SDRAMC, 0xec094060 11*a373024eSAngelo Dureghello.equ MISCCR2, 0xec09001a 12*a373024eSAngelo Dureghello.equ DDR_RCR, 0xfc0b8180 13*a373024eSAngelo Dureghello.equ DDR_PADCR, 0xfc0b81ac 14*a373024eSAngelo Dureghello.equ DDR_CR00, 0xfc0b8000 15*a373024eSAngelo Dureghello.equ DDR_CR06, 0xfc0b8018 16*a373024eSAngelo Dureghello.equ DDR_CR09, 0xfc0b8024 17*a373024eSAngelo Dureghello.equ DDR_CR40, 0xfc0b80a0 18*a373024eSAngelo Dureghello.equ DDR_CR45, 0xfc0b80b4 19*a373024eSAngelo Dureghello.equ DDR_CR56, 0xfc0b80e0 20*a373024eSAngelo Dureghello 21*a373024eSAngelo Dureghello.global sbf_dram_init 22*a373024eSAngelo Dureghello.text 23*a373024eSAngelo Dureghello 24*a373024eSAngelo Dureghellosbf_dram_init: 25*a373024eSAngelo Dureghello /* CD46 = DDR on */ 26*a373024eSAngelo Dureghello move.l #PPMCR0, %a1 27*a373024eSAngelo Dureghello move.b #46, (%a1) 28*a373024eSAngelo Dureghello 29*a373024eSAngelo Dureghello /* stmark 2, max drive strength */ 30*a373024eSAngelo Dureghello move.l #MSCR_SDRAMC, %a1 31*a373024eSAngelo Dureghello move.b #1, (%a1) 32*a373024eSAngelo Dureghello 33*a373024eSAngelo Dureghello /* 34*a373024eSAngelo Dureghello * use cpu clock, seems more realiable 35*a373024eSAngelo Dureghello * 36*a373024eSAngelo Dureghello * DDR2 clock is serviced from DDR controller as input clock / 2 37*a373024eSAngelo Dureghello * so, if clock comes from 38*a373024eSAngelo Dureghello * vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured) 39*a373024eSAngelo Dureghello * cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured) 40*a373024eSAngelo Dureghello * 41*a373024eSAngelo Dureghello * . 42*a373024eSAngelo Dureghello * / \ DDR2 can't be clocked lower than 125Mhz 43*a373024eSAngelo Dureghello * / ! \ DDR2 init must pass further i/dcache enable test 44*a373024eSAngelo Dureghello * /_____\ 45*a373024eSAngelo Dureghello * WARNING 46*a373024eSAngelo Dureghello */ 47*a373024eSAngelo Dureghello 48*a373024eSAngelo Dureghello /* cpu / 2 = 125 Mhz for 480 Mhz pll */ 49*a373024eSAngelo Dureghello move.l #MISCCR2, %a1 50*a373024eSAngelo Dureghello move.w #0xa01d, (%a1) 51*a373024eSAngelo Dureghello 52*a373024eSAngelo Dureghello /* DDR force sw reset settings */ 53*a373024eSAngelo Dureghello move.l #DDR_RCR, %a1 54*a373024eSAngelo Dureghello move.l #0x00000000, (%a1) 55*a373024eSAngelo Dureghello move.l #0x40000000, (%a1) 56*a373024eSAngelo Dureghello 57*a373024eSAngelo Dureghello /* 58*a373024eSAngelo Dureghello * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good, 59*a373024eSAngelo Dureghello * 500/700 mV are ok 60*a373024eSAngelo Dureghello */ 61*a373024eSAngelo Dureghello move.l #DDR_PADCR, %a1 62*a373024eSAngelo Dureghello move.l #0x01030203, (%a1) /* as freescale tower */ 63*a373024eSAngelo Dureghello 64*a373024eSAngelo Dureghello move.l #DDR_CR00, %a1 65*a373024eSAngelo Dureghello move.l #0x01010101, (%a1)+ /* 0x00 */ 66*a373024eSAngelo Dureghello move.l #0x00000101, (%a1)+ /* 0x04 */ 67*a373024eSAngelo Dureghello move.l #0x01010100, (%a1)+ /* 0x08 */ 68*a373024eSAngelo Dureghello move.l #0x01010000, (%a1)+ /* 0x0C */ 69*a373024eSAngelo Dureghello move.l #0x00010101, (%a1)+ /* 0x10 */ 70*a373024eSAngelo Dureghello move.l #DDR_CR06, %a1 71*a373024eSAngelo Dureghello move.l #0x00010100, (%a1)+ /* 0x18 */ 72*a373024eSAngelo Dureghello move.l #0x00000001, (%a1)+ /* 0x1C */ 73*a373024eSAngelo Dureghello move.l #0x01000001, (%a1)+ /* 0x20 */ 74*a373024eSAngelo Dureghello move.l #0x00000100, (%a1)+ /* 0x24 */ 75*a373024eSAngelo Dureghello move.l #0x00010001, (%a1)+ /* 0x28 */ 76*a373024eSAngelo Dureghello move.l #0x00000200, (%a1)+ /* 0x2C */ 77*a373024eSAngelo Dureghello move.l #0x01000002, (%a1)+ /* 0x30 */ 78*a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x34 */ 79*a373024eSAngelo Dureghello move.l #0x00000100, (%a1)+ /* 0x38 */ 80*a373024eSAngelo Dureghello move.l #0x02000100, (%a1)+ /* 0x3C */ 81*a373024eSAngelo Dureghello move.l #0x02000407, (%a1)+ /* 0x40 */ 82*a373024eSAngelo Dureghello move.l #0x02030007, (%a1)+ /* 0x44 */ 83*a373024eSAngelo Dureghello move.l #0x02000100, (%a1)+ /* 0x48 */ 84*a373024eSAngelo Dureghello move.l #0x0A030203, (%a1)+ /* 0x4C */ 85*a373024eSAngelo Dureghello move.l #0x00020708, (%a1)+ /* 0x50 */ 86*a373024eSAngelo Dureghello move.l #0x00050008, (%a1)+ /* 0x54 */ 87*a373024eSAngelo Dureghello move.l #0x04030002, (%a1)+ /* 0x58 */ 88*a373024eSAngelo Dureghello move.l #0x00000004, (%a1)+ /* 0x5C */ 89*a373024eSAngelo Dureghello move.l #0x020A0000, (%a1)+ /* 0x60 */ 90*a373024eSAngelo Dureghello move.l #0x0C00000E, (%a1)+ /* 0x64 */ 91*a373024eSAngelo Dureghello move.l #0x00002004, (%a1)+ /* 0x68 */ 92*a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x6C */ 93*a373024eSAngelo Dureghello move.l #0x00100010, (%a1)+ /* 0x70 */ 94*a373024eSAngelo Dureghello move.l #0x00100010, (%a1)+ /* 0x74 */ 95*a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0x78 */ 96*a373024eSAngelo Dureghello move.l #0x07990000, (%a1)+ /* 0x7C */ 97*a373024eSAngelo Dureghello move.l #DDR_CR40, %a1 98*a373024eSAngelo Dureghello move.l #0x00000000, (%a1)+ /* 0xA0 */ 99*a373024eSAngelo Dureghello move.l #0x00C80064, (%a1)+ /* 0xA4 */ 100*a373024eSAngelo Dureghello move.l #0x44520002, (%a1)+ /* 0xA8 */ 101*a373024eSAngelo Dureghello move.l #0x00C80023, (%a1)+ /* 0xAC */ 102*a373024eSAngelo Dureghello move.l #DDR_CR45, %a1 103*a373024eSAngelo Dureghello move.l #0x0000C350, (%a1) /* 0xB4 */ 104*a373024eSAngelo Dureghello move.l #DDR_CR56, %a1 105*a373024eSAngelo Dureghello move.l #0x04000000, (%a1)+ /* 0xE0 */ 106*a373024eSAngelo Dureghello move.l #0x03000304, (%a1)+ /* 0xE4 */ 107*a373024eSAngelo Dureghello move.l #0x40040000, (%a1)+ /* 0xE8 */ 108*a373024eSAngelo Dureghello move.l #0xC0004004, (%a1)+ /* 0xEC */ 109*a373024eSAngelo Dureghello move.l #0x0642C000, (%a1)+ /* 0xF0 */ 110*a373024eSAngelo Dureghello move.l #0x00000642, (%a1)+ /* 0xF4 */ 111*a373024eSAngelo Dureghello move.l #DDR_CR09, %a1 112*a373024eSAngelo Dureghello tpf 113*a373024eSAngelo Dureghello move.l #0x01000100, (%a1) /* 0x24 */ 114*a373024eSAngelo Dureghello 115*a373024eSAngelo Dureghello move.l #0x2000, %d1 116*a373024eSAngelo Dureghello bsr asm_delay 117*a373024eSAngelo Dureghello 118*a373024eSAngelo Dureghello 119*a373024eSAngelo Dureghello rts 120