1*67482f57SAlexey Brodkin /* 2*67482f57SAlexey Brodkin * Copyright (C) 2017 Synopsys, Inc. All rights reserved. 3*67482f57SAlexey Brodkin * 4*67482f57SAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 5*67482f57SAlexey Brodkin */ 6*67482f57SAlexey Brodkin 7*67482f57SAlexey Brodkin #include <common.h> 8*67482f57SAlexey Brodkin #include <dwmmc.h> 9*67482f57SAlexey Brodkin #include <malloc.h> 10*67482f57SAlexey Brodkin 11*67482f57SAlexey Brodkin DECLARE_GLOBAL_DATA_PTR; 12*67482f57SAlexey Brodkin 13*67482f57SAlexey Brodkin #define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000) 14*67482f57SAlexey Brodkin #define CREG_PAE (CREG_BASE + 0x180) 15*67482f57SAlexey Brodkin #define CREG_PAE_UPDATE (CREG_BASE + 0x194) 16*67482f57SAlexey Brodkin #define CREG_CPU_START (CREG_BASE + 0x400) 17*67482f57SAlexey Brodkin 18*67482f57SAlexey Brodkin int board_early_init_f(void) 19*67482f57SAlexey Brodkin { 20*67482f57SAlexey Brodkin /* In current chip PAE support for DMA is broken, disabling it. */ 21*67482f57SAlexey Brodkin writel(0, (void __iomem *) CREG_PAE); 22*67482f57SAlexey Brodkin 23*67482f57SAlexey Brodkin /* Really apply settings made above */ 24*67482f57SAlexey Brodkin writel(1, (void __iomem *) CREG_PAE_UPDATE); 25*67482f57SAlexey Brodkin 26*67482f57SAlexey Brodkin return 0; 27*67482f57SAlexey Brodkin } 28*67482f57SAlexey Brodkin 29*67482f57SAlexey Brodkin int board_mmc_init(bd_t *bis) 30*67482f57SAlexey Brodkin { 31*67482f57SAlexey Brodkin struct dwmci_host *host = NULL; 32*67482f57SAlexey Brodkin 33*67482f57SAlexey Brodkin host = malloc(sizeof(struct dwmci_host)); 34*67482f57SAlexey Brodkin if (!host) { 35*67482f57SAlexey Brodkin printf("dwmci_host malloc fail!\n"); 36*67482f57SAlexey Brodkin return 1; 37*67482f57SAlexey Brodkin } 38*67482f57SAlexey Brodkin 39*67482f57SAlexey Brodkin memset(host, 0, sizeof(struct dwmci_host)); 40*67482f57SAlexey Brodkin host->name = "Synopsys Mobile storage"; 41*67482f57SAlexey Brodkin host->ioaddr = (void *)ARC_DWMMC_BASE; 42*67482f57SAlexey Brodkin host->buswidth = 4; 43*67482f57SAlexey Brodkin host->dev_index = 0; 44*67482f57SAlexey Brodkin host->bus_hz = 100000000; 45*67482f57SAlexey Brodkin 46*67482f57SAlexey Brodkin add_dwmci(host, host->bus_hz / 2, 400000); 47*67482f57SAlexey Brodkin 48*67482f57SAlexey Brodkin return 0; 49*67482f57SAlexey Brodkin } 50*67482f57SAlexey Brodkin 51*67482f57SAlexey Brodkin #define RESET_VECTOR_ADDR 0x0 52*67482f57SAlexey Brodkin 53*67482f57SAlexey Brodkin void smp_set_core_boot_addr(unsigned long addr, int corenr) 54*67482f57SAlexey Brodkin { 55*67482f57SAlexey Brodkin /* All cores have reset vector pointing to 0 */ 56*67482f57SAlexey Brodkin writel(addr, (void __iomem *)RESET_VECTOR_ADDR); 57*67482f57SAlexey Brodkin 58*67482f57SAlexey Brodkin /* Make sure other cores see written value in memory */ 59*67482f57SAlexey Brodkin flush_dcache_all(); 60*67482f57SAlexey Brodkin } 61*67482f57SAlexey Brodkin 62*67482f57SAlexey Brodkin void smp_kick_all_cpus(void) 63*67482f57SAlexey Brodkin { 64*67482f57SAlexey Brodkin #define BITS_START_CORE1 1 65*67482f57SAlexey Brodkin #define BITS_START_CORE2 2 66*67482f57SAlexey Brodkin #define BITS_START_CORE3 3 67*67482f57SAlexey Brodkin 68*67482f57SAlexey Brodkin int cmd = readl((void __iomem *)CREG_CPU_START); 69*67482f57SAlexey Brodkin 70*67482f57SAlexey Brodkin cmd |= (1 << BITS_START_CORE1) | 71*67482f57SAlexey Brodkin (1 << BITS_START_CORE2) | 72*67482f57SAlexey Brodkin (1 << BITS_START_CORE3); 73*67482f57SAlexey Brodkin writel(cmd, (void __iomem *)CREG_CPU_START); 74*67482f57SAlexey Brodkin } 75