165fcba12SAlexey Brodkin /* 265fcba12SAlexey Brodkin * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. 365fcba12SAlexey Brodkin * 465fcba12SAlexey Brodkin * SPDX-License-Identifier: GPL-2.0+ 565fcba12SAlexey Brodkin */ 665fcba12SAlexey Brodkin 765fcba12SAlexey Brodkin #include <common.h> 865fcba12SAlexey Brodkin #include <dwmmc.h> 965fcba12SAlexey Brodkin #include <malloc.h> 1065fcba12SAlexey Brodkin #include "axs10x.h" 1165fcba12SAlexey Brodkin 1265fcba12SAlexey Brodkin DECLARE_GLOBAL_DATA_PTR; 1365fcba12SAlexey Brodkin 1465fcba12SAlexey Brodkin int board_mmc_init(bd_t *bis) 1565fcba12SAlexey Brodkin { 1665fcba12SAlexey Brodkin struct dwmci_host *host = NULL; 1765fcba12SAlexey Brodkin 1865fcba12SAlexey Brodkin host = malloc(sizeof(struct dwmci_host)); 1965fcba12SAlexey Brodkin if (!host) { 2065fcba12SAlexey Brodkin printf("dwmci_host malloc fail!\n"); 2165fcba12SAlexey Brodkin return 1; 2265fcba12SAlexey Brodkin } 2365fcba12SAlexey Brodkin 2465fcba12SAlexey Brodkin memset(host, 0, sizeof(struct dwmci_host)); 2565fcba12SAlexey Brodkin host->name = "Synopsys Mobile storage"; 2665fcba12SAlexey Brodkin host->ioaddr = (void *)ARC_DWMMC_BASE; 2765fcba12SAlexey Brodkin host->buswidth = 4; 2865fcba12SAlexey Brodkin host->dev_index = 0; 2965fcba12SAlexey Brodkin host->bus_hz = 50000000; 3065fcba12SAlexey Brodkin 3165fcba12SAlexey Brodkin add_dwmci(host, host->bus_hz / 2, 400000); 3265fcba12SAlexey Brodkin 3365fcba12SAlexey Brodkin return 0; 3465fcba12SAlexey Brodkin } 3565fcba12SAlexey Brodkin 3665fcba12SAlexey Brodkin #define AXS_MB_CREG 0xE0011000 3765fcba12SAlexey Brodkin 3865fcba12SAlexey Brodkin int board_early_init_f(void) 3965fcba12SAlexey Brodkin { 4065fcba12SAlexey Brodkin if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28)) 4165fcba12SAlexey Brodkin gd->board_type = AXS_MB_V3; 4265fcba12SAlexey Brodkin else 4365fcba12SAlexey Brodkin gd->board_type = AXS_MB_V2; 4465fcba12SAlexey Brodkin 4565fcba12SAlexey Brodkin return 0; 4665fcba12SAlexey Brodkin } 4765fcba12SAlexey Brodkin 4865fcba12SAlexey Brodkin #ifdef CONFIG_ISA_ARCV2 4965fcba12SAlexey Brodkin #define RESET_VECTOR_ADDR 0x0 5065fcba12SAlexey Brodkin 5165fcba12SAlexey Brodkin void smp_set_core_boot_addr(unsigned long addr, int corenr) 5265fcba12SAlexey Brodkin { 5365fcba12SAlexey Brodkin /* All cores have reset vector pointing to 0 */ 5465fcba12SAlexey Brodkin writel(addr, (void __iomem *)RESET_VECTOR_ADDR); 5565fcba12SAlexey Brodkin 5665fcba12SAlexey Brodkin /* Make sure other cores see written value in memory */ 5765fcba12SAlexey Brodkin flush_dcache_all(); 5865fcba12SAlexey Brodkin } 5965fcba12SAlexey Brodkin 6065fcba12SAlexey Brodkin void smp_kick_all_cpus(void) 6165fcba12SAlexey Brodkin { 6265fcba12SAlexey Brodkin /* CPU start CREG */ 6365fcba12SAlexey Brodkin #define AXC003_CREG_CPU_START 0xF0001400 6465fcba12SAlexey Brodkin /* Bits positions in CPU start CREG */ 6565fcba12SAlexey Brodkin #define BITS_START 0 66*0b0db98bSAlexey Brodkin #define BITS_START_MODE 4 6765fcba12SAlexey Brodkin #define BITS_CORE_SEL 9 6865fcba12SAlexey Brodkin 69*0b0db98bSAlexey Brodkin int cmd = readl((void __iomem *)AXC003_CREG_CPU_START); 70*0b0db98bSAlexey Brodkin cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START); 71*0b0db98bSAlexey Brodkin cmd &= ~(1 << BITS_START_MODE); 72*0b0db98bSAlexey Brodkin writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); 7365fcba12SAlexey Brodkin } 7465fcba12SAlexey Brodkin #endif 75