15835823dSIan Campbell #include <common.h> 25835823dSIan Campbell #include <netdev.h> 35835823dSIan Campbell #include <miiphy.h> 45835823dSIan Campbell #include <asm/gpio.h> 55835823dSIan Campbell #include <asm/io.h> 65835823dSIan Campbell #include <asm/arch/clock.h> 75835823dSIan Campbell #include <asm/arch/gpio.h> 85835823dSIan Campbell 95835823dSIan Campbell int sunxi_gmac_initialize(bd_t *bis) 105835823dSIan Campbell { 115835823dSIan Campbell int pin; 125835823dSIan Campbell struct sunxi_ccm_reg *const ccm = 135835823dSIan Campbell (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 145835823dSIan Campbell 155835823dSIan Campbell /* Set up clock gating */ 16eafec320SHans de Goede #ifndef CONFIG_MACH_SUN6I 175835823dSIan Campbell setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); 18eafec320SHans de Goede #else 19eafec320SHans de Goede setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); 20eafec320SHans de Goede setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); 21eafec320SHans de Goede #endif 225835823dSIan Campbell 235835823dSIan Campbell /* Set MII clock */ 24ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 255835823dSIan Campbell setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | 265835823dSIan Campbell CCM_GMAC_CTRL_GPIT_RGMII); 27*c13f60d9SHans de Goede setbits_le32(&ccm->gmac_clk_cfg, 28*c13f60d9SHans de Goede CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); 29ef7e723bSChen-Yu Tsai #else 30ef7e723bSChen-Yu Tsai setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | 31ef7e723bSChen-Yu Tsai CCM_GMAC_CTRL_GPIT_MII); 32ef7e723bSChen-Yu Tsai #endif 335835823dSIan Campbell 34eafec320SHans de Goede #ifndef CONFIG_MACH_SUN6I 355835823dSIan Campbell /* Configure pin mux settings for GMAC */ 365835823dSIan Campbell for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { 37ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 385835823dSIan Campbell /* skip unused pins in RGMII mode */ 395835823dSIan Campbell if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14)) 405835823dSIan Campbell continue; 41ef7e723bSChen-Yu Tsai #endif 425835823dSIan Campbell sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC); 435835823dSIan Campbell sunxi_gpio_set_drv(pin, 3); 445835823dSIan Campbell } 45eafec320SHans de Goede #elif defined CONFIG_RGMII 46eafec320SHans de Goede /* Configure sun6i RGMII mode pin mux settings */ 47eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) { 48eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 49eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3); 50eafec320SHans de Goede } 51eafec320SHans de Goede for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 52eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 53eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3); 54eafec320SHans de Goede } 55eafec320SHans de Goede for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) { 56eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 57eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3); 58eafec320SHans de Goede } 59eafec320SHans de Goede for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) { 60eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 61eafec320SHans de Goede sunxi_gpio_set_drv(pin, 3); 62eafec320SHans de Goede } 63eafec320SHans de Goede #elif defined CONFIG_GMII 64eafec320SHans de Goede /* Configure sun6i GMII mode pin mux settings */ 65eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) { 66eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 67eafec320SHans de Goede sunxi_gpio_set_drv(pin, 2); 68eafec320SHans de Goede } 69eafec320SHans de Goede #else 70eafec320SHans de Goede /* Configure sun6i MII mode pin mux settings */ 71eafec320SHans de Goede for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) 72eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 73eafec320SHans de Goede for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++) 74eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 75eafec320SHans de Goede for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++) 76eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 77eafec320SHans de Goede for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++) 78eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 79eafec320SHans de Goede for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++) 80eafec320SHans de Goede sunxi_gpio_set_cfgpin(pin, SUN6I_GPA0_GMAC); 81eafec320SHans de Goede #endif 825835823dSIan Campbell 83ef7e723bSChen-Yu Tsai #ifdef CONFIG_RGMII 845835823dSIan Campbell return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII); 85eafec320SHans de Goede #elif defined CONFIG_GMII 86eafec320SHans de Goede return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_GMII); 87ef7e723bSChen-Yu Tsai #else 88ef7e723bSChen-Yu Tsai return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII); 89ef7e723bSChen-Yu Tsai #endif 905835823dSIan Campbell } 91