1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/usb_phy.h> 24 #include <asm/gpio.h> 25 #include <asm/io.h> 26 #include <nand.h> 27 #include <net.h> 28 #include <sy8106a.h> 29 30 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 31 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 32 int soft_i2c_gpio_sda; 33 int soft_i2c_gpio_scl; 34 35 static int soft_i2c_board_init(void) 36 { 37 int ret; 38 39 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 40 if (soft_i2c_gpio_sda < 0) { 41 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 42 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 43 return soft_i2c_gpio_sda; 44 } 45 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 46 if (ret) { 47 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 49 return ret; 50 } 51 52 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 53 if (soft_i2c_gpio_scl < 0) { 54 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 56 return soft_i2c_gpio_scl; 57 } 58 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 59 if (ret) { 60 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 62 return ret; 63 } 64 65 return 0; 66 } 67 #else 68 static int soft_i2c_board_init(void) { return 0; } 69 #endif 70 71 DECLARE_GLOBAL_DATA_PTR; 72 73 /* add board specific code here */ 74 int board_init(void) 75 { 76 int id_pfr1, ret; 77 78 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 79 80 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 81 debug("id_pfr1: 0x%08x\n", id_pfr1); 82 /* Generic Timer Extension available? */ 83 if ((id_pfr1 >> 16) & 0xf) { 84 debug("Setting CNTFRQ\n"); 85 /* CNTFRQ == 24 MHz */ 86 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 87 } 88 89 ret = axp_gpio_init(); 90 if (ret) 91 return ret; 92 93 #ifdef CONFIG_MACPWR 94 gpio_request(CONFIG_MACPWR, "macpwr"); 95 gpio_direction_output(CONFIG_MACPWR, 1); 96 #endif 97 98 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 99 return soft_i2c_board_init(); 100 } 101 102 int dram_init(void) 103 { 104 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 105 106 return 0; 107 } 108 109 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 110 static void nand_pinmux_setup(void) 111 { 112 unsigned int pin; 113 114 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 115 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 116 117 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 118 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 119 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 120 #endif 121 /* sun4i / sun7i do have a PC23, but it is not used for nand, 122 * only sun7i has a PC24 */ 123 #ifdef CONFIG_MACH_SUN7I 124 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 125 #endif 126 } 127 128 static void nand_clock_setup(void) 129 { 130 struct sunxi_ccm_reg *const ccm = 131 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 132 133 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 134 #ifdef CONFIG_MACH_SUN9I 135 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 136 #else 137 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 138 #endif 139 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 140 } 141 142 void board_nand_init(void) 143 { 144 nand_pinmux_setup(); 145 nand_clock_setup(); 146 } 147 #endif 148 149 #ifdef CONFIG_GENERIC_MMC 150 static void mmc_pinmux_setup(int sdc) 151 { 152 unsigned int pin; 153 __maybe_unused int pins; 154 155 switch (sdc) { 156 case 0: 157 /* SDC0: PF0-PF5 */ 158 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 159 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 160 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 161 sunxi_gpio_set_drv(pin, 2); 162 } 163 break; 164 165 case 1: 166 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 167 168 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 169 if (pins == SUNXI_GPIO_H) { 170 /* SDC1: PH22-PH-27 */ 171 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 172 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 173 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 174 sunxi_gpio_set_drv(pin, 2); 175 } 176 } else { 177 /* SDC1: PG0-PG5 */ 178 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 179 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 180 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 181 sunxi_gpio_set_drv(pin, 2); 182 } 183 } 184 #elif defined(CONFIG_MACH_SUN5I) 185 /* SDC1: PG3-PG8 */ 186 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 187 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 188 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 189 sunxi_gpio_set_drv(pin, 2); 190 } 191 #elif defined(CONFIG_MACH_SUN6I) 192 /* SDC1: PG0-PG5 */ 193 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 194 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 195 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 196 sunxi_gpio_set_drv(pin, 2); 197 } 198 #elif defined(CONFIG_MACH_SUN8I) 199 if (pins == SUNXI_GPIO_D) { 200 /* SDC1: PD2-PD7 */ 201 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 202 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 203 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 204 sunxi_gpio_set_drv(pin, 2); 205 } 206 } else { 207 /* SDC1: PG0-PG5 */ 208 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 209 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 210 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 211 sunxi_gpio_set_drv(pin, 2); 212 } 213 } 214 #endif 215 break; 216 217 case 2: 218 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 219 220 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 221 /* SDC2: PC6-PC11 */ 222 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 223 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 224 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 225 sunxi_gpio_set_drv(pin, 2); 226 } 227 #elif defined(CONFIG_MACH_SUN5I) 228 if (pins == SUNXI_GPIO_E) { 229 /* SDC2: PE4-PE9 */ 230 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 231 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 232 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 233 sunxi_gpio_set_drv(pin, 2); 234 } 235 } else { 236 /* SDC2: PC6-PC15 */ 237 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 238 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 239 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 240 sunxi_gpio_set_drv(pin, 2); 241 } 242 } 243 #elif defined(CONFIG_MACH_SUN6I) 244 if (pins == SUNXI_GPIO_A) { 245 /* SDC2: PA9-PA14 */ 246 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 247 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 248 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 249 sunxi_gpio_set_drv(pin, 2); 250 } 251 } else { 252 /* SDC2: PC6-PC15, PC24 */ 253 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 254 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 255 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 256 sunxi_gpio_set_drv(pin, 2); 257 } 258 259 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 260 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 261 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 262 } 263 #elif defined(CONFIG_MACH_SUN8I) 264 /* SDC2: PC5-PC6, PC8-PC16 */ 265 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 266 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 267 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 268 sunxi_gpio_set_drv(pin, 2); 269 } 270 271 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 272 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 273 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 274 sunxi_gpio_set_drv(pin, 2); 275 } 276 #endif 277 break; 278 279 case 3: 280 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 281 282 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 283 /* SDC3: PI4-PI9 */ 284 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 285 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 286 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 287 sunxi_gpio_set_drv(pin, 2); 288 } 289 #elif defined(CONFIG_MACH_SUN6I) 290 if (pins == SUNXI_GPIO_A) { 291 /* SDC3: PA9-PA14 */ 292 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 293 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 294 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 295 sunxi_gpio_set_drv(pin, 2); 296 } 297 } else { 298 /* SDC3: PC6-PC15, PC24 */ 299 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 300 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 301 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 302 sunxi_gpio_set_drv(pin, 2); 303 } 304 305 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 306 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 307 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 308 } 309 #endif 310 break; 311 312 default: 313 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 314 break; 315 } 316 } 317 318 int board_mmc_init(bd_t *bis) 319 { 320 __maybe_unused struct mmc *mmc0, *mmc1; 321 __maybe_unused char buf[512]; 322 323 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 324 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 325 if (!mmc0) 326 return -1; 327 328 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 329 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 330 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 331 if (!mmc1) 332 return -1; 333 #endif 334 335 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 336 /* 337 * On systems with an emmc (mmc2), figure out if we are booting from 338 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 339 * are searched there first. Note we only do this for u-boot proper, 340 * not for the SPL, see spl_boot_device(). 341 */ 342 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 343 sunxi_mmc_has_egon_boot_signature(mmc1)) { 344 /* Booting from emmc / mmc2, swap */ 345 mmc0->block_dev.devnum = 1; 346 mmc1->block_dev.devnum = 0; 347 } 348 #endif 349 350 return 0; 351 } 352 #endif 353 354 void i2c_init_board(void) 355 { 356 #ifdef CONFIG_I2C0_ENABLE 357 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 358 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 359 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 360 clock_twi_onoff(0, 1); 361 #elif defined(CONFIG_MACH_SUN6I) 362 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 363 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 364 clock_twi_onoff(0, 1); 365 #elif defined(CONFIG_MACH_SUN8I) 366 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 367 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 368 clock_twi_onoff(0, 1); 369 #endif 370 #endif 371 372 #ifdef CONFIG_I2C1_ENABLE 373 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 374 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 375 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 376 clock_twi_onoff(1, 1); 377 #elif defined(CONFIG_MACH_SUN5I) 378 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 379 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 380 clock_twi_onoff(1, 1); 381 #elif defined(CONFIG_MACH_SUN6I) 382 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 383 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 384 clock_twi_onoff(1, 1); 385 #elif defined(CONFIG_MACH_SUN8I) 386 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 387 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 388 clock_twi_onoff(1, 1); 389 #endif 390 #endif 391 392 #ifdef CONFIG_I2C2_ENABLE 393 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 394 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 395 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 396 clock_twi_onoff(2, 1); 397 #elif defined(CONFIG_MACH_SUN5I) 398 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 399 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 400 clock_twi_onoff(2, 1); 401 #elif defined(CONFIG_MACH_SUN6I) 402 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 403 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 404 clock_twi_onoff(2, 1); 405 #elif defined(CONFIG_MACH_SUN8I) 406 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 407 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 408 clock_twi_onoff(2, 1); 409 #endif 410 #endif 411 412 #ifdef CONFIG_I2C3_ENABLE 413 #if defined(CONFIG_MACH_SUN6I) 414 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 415 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 416 clock_twi_onoff(3, 1); 417 #elif defined(CONFIG_MACH_SUN7I) 418 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 419 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 420 clock_twi_onoff(3, 1); 421 #endif 422 #endif 423 424 #ifdef CONFIG_I2C4_ENABLE 425 #if defined(CONFIG_MACH_SUN7I) 426 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 427 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 428 clock_twi_onoff(4, 1); 429 #endif 430 #endif 431 432 #ifdef CONFIG_R_I2C_ENABLE 433 clock_twi_onoff(5, 1); 434 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 435 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 436 #endif 437 } 438 439 #ifdef CONFIG_SPL_BUILD 440 void sunxi_board_init(void) 441 { 442 int power_failed = 0; 443 unsigned long ramsize; 444 445 #ifdef CONFIG_SY8106A_POWER 446 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 447 #endif 448 449 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 450 defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 451 power_failed = axp_init(); 452 453 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 454 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 455 #endif 456 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 457 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 458 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 459 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 460 #endif 461 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 462 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 463 #endif 464 465 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER 466 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 467 #endif 468 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 469 #if !defined(CONFIG_AXP152_POWER) 470 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 471 #endif 472 #ifdef CONFIG_AXP209_POWER 473 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 474 #endif 475 476 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER) 477 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 478 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 479 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 480 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 481 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 482 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 483 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 484 #endif 485 #endif 486 printf("DRAM:"); 487 ramsize = sunxi_dram_init(); 488 printf(" %lu MiB\n", ramsize >> 20); 489 if (!ramsize) 490 hang(); 491 492 /* 493 * Only clock up the CPU to full speed if we are reasonably 494 * assured it's being powered with suitable core voltage 495 */ 496 if (!power_failed) 497 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 498 else 499 printf("Failed to set core voltage! Can't set CPU frequency\n"); 500 } 501 #endif 502 503 #ifdef CONFIG_USB_GADGET 504 int g_dnl_board_usb_cable_connected(void) 505 { 506 return sunxi_usb_phy_vbus_detect(0); 507 } 508 #endif 509 510 #ifdef CONFIG_SERIAL_TAG 511 void get_board_serial(struct tag_serialnr *serialnr) 512 { 513 char *serial_string; 514 unsigned long long serial; 515 516 serial_string = getenv("serial#"); 517 518 if (serial_string) { 519 serial = simple_strtoull(serial_string, NULL, 16); 520 521 serialnr->high = (unsigned int) (serial >> 32); 522 serialnr->low = (unsigned int) (serial & 0xffffffff); 523 } else { 524 serialnr->high = 0; 525 serialnr->low = 0; 526 } 527 } 528 #endif 529 530 #if !defined(CONFIG_SPL_BUILD) 531 #include <asm/arch/spl.h> 532 533 /* 534 * Check the SPL header for the "sunxi" variant. If found: parse values 535 * that might have been passed by the loader ("fel" utility), and update 536 * the environment accordingly. 537 */ 538 static void parse_spl_header(const uint32_t spl_addr) 539 { 540 struct boot_file_head *spl = (void *)spl_addr; 541 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { 542 uint8_t spl_header_version = spl->spl_signature[3]; 543 if (spl_header_version == SPL_HEADER_VERSION) { 544 if (spl->fel_script_address) 545 setenv_hex("fel_scriptaddr", 546 spl->fel_script_address); 547 return; 548 } 549 printf("sunxi SPL version mismatch: expected %u, got %u\n", 550 SPL_HEADER_VERSION, spl_header_version); 551 } 552 } 553 #endif 554 555 #ifdef CONFIG_MISC_INIT_R 556 int misc_init_r(void) 557 { 558 char serial_string[17] = { 0 }; 559 unsigned int sid[4]; 560 uint8_t mac_addr[6]; 561 int ret; 562 563 #if !defined(CONFIG_SPL_BUILD) 564 setenv("fel_booted", NULL); 565 setenv("fel_scriptaddr", NULL); 566 /* determine if we are running in FEL mode */ 567 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 568 setenv("fel_booted", "1"); 569 parse_spl_header(SPL_ADDR); 570 } 571 #endif 572 573 ret = sunxi_get_sid(sid); 574 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 575 if (!getenv("ethaddr")) { 576 /* Non OUI / registered MAC address */ 577 mac_addr[0] = 0x02; 578 mac_addr[1] = (sid[0] >> 0) & 0xff; 579 mac_addr[2] = (sid[3] >> 24) & 0xff; 580 mac_addr[3] = (sid[3] >> 16) & 0xff; 581 mac_addr[4] = (sid[3] >> 8) & 0xff; 582 mac_addr[5] = (sid[3] >> 0) & 0xff; 583 584 eth_setenv_enetaddr("ethaddr", mac_addr); 585 } 586 587 if (!getenv("serial#")) { 588 snprintf(serial_string, sizeof(serial_string), 589 "%08x%08x", sid[0], sid[3]); 590 591 setenv("serial#", serial_string); 592 } 593 } 594 595 #ifndef CONFIG_MACH_SUN9I 596 ret = sunxi_usb_phy_probe(); 597 if (ret) 598 return ret; 599 #endif 600 sunxi_musb_board_init(); 601 602 return 0; 603 } 604 #endif 605 606 #ifdef CONFIG_OF_BOARD_SETUP 607 int ft_board_setup(void *blob, bd_t *bd) 608 { 609 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 610 return sunxi_simplefb_setup(blob); 611 #endif 612 } 613 #endif /* CONFIG_OF_BOARD_SETUP */ 614