1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/spl.h> 24 #include <asm/arch/usb_phy.h> 25 #ifndef CONFIG_ARM64 26 #include <asm/armv7.h> 27 #endif 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <crc.h> 31 #include <environment.h> 32 #include <libfdt.h> 33 #include <nand.h> 34 #include <net.h> 35 #include <sy8106a.h> 36 37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 39 int soft_i2c_gpio_sda; 40 int soft_i2c_gpio_scl; 41 42 static int soft_i2c_board_init(void) 43 { 44 int ret; 45 46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 47 if (soft_i2c_gpio_sda < 0) { 48 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 50 return soft_i2c_gpio_sda; 51 } 52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 53 if (ret) { 54 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 56 return ret; 57 } 58 59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 60 if (soft_i2c_gpio_scl < 0) { 61 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 63 return soft_i2c_gpio_scl; 64 } 65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 66 if (ret) { 67 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 69 return ret; 70 } 71 72 return 0; 73 } 74 #else 75 static int soft_i2c_board_init(void) { return 0; } 76 #endif 77 78 DECLARE_GLOBAL_DATA_PTR; 79 80 void i2c_init_board(void) 81 { 82 #ifdef CONFIG_I2C0_ENABLE 83 #if defined(CONFIG_MACH_SUN4I) || \ 84 defined(CONFIG_MACH_SUN5I) || \ 85 defined(CONFIG_MACH_SUN7I) || \ 86 defined(CONFIG_MACH_SUN8I_R40) 87 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 88 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 89 clock_twi_onoff(0, 1); 90 #elif defined(CONFIG_MACH_SUN6I) 91 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 92 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 93 clock_twi_onoff(0, 1); 94 #elif defined(CONFIG_MACH_SUN8I) 95 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 96 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 97 clock_twi_onoff(0, 1); 98 #endif 99 #endif 100 101 #ifdef CONFIG_I2C1_ENABLE 102 #if defined(CONFIG_MACH_SUN4I) || \ 103 defined(CONFIG_MACH_SUN7I) || \ 104 defined(CONFIG_MACH_SUN8I_R40) 105 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 106 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 107 clock_twi_onoff(1, 1); 108 #elif defined(CONFIG_MACH_SUN5I) 109 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 110 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 111 clock_twi_onoff(1, 1); 112 #elif defined(CONFIG_MACH_SUN6I) 113 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 114 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 115 clock_twi_onoff(1, 1); 116 #elif defined(CONFIG_MACH_SUN8I) 117 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 118 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 119 clock_twi_onoff(1, 1); 120 #endif 121 #endif 122 123 #ifdef CONFIG_I2C2_ENABLE 124 #if defined(CONFIG_MACH_SUN4I) || \ 125 defined(CONFIG_MACH_SUN7I) || \ 126 defined(CONFIG_MACH_SUN8I_R40) 127 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 128 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 129 clock_twi_onoff(2, 1); 130 #elif defined(CONFIG_MACH_SUN5I) 131 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 132 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 133 clock_twi_onoff(2, 1); 134 #elif defined(CONFIG_MACH_SUN6I) 135 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 136 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 137 clock_twi_onoff(2, 1); 138 #elif defined(CONFIG_MACH_SUN8I) 139 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 140 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 141 clock_twi_onoff(2, 1); 142 #endif 143 #endif 144 145 #ifdef CONFIG_I2C3_ENABLE 146 #if defined(CONFIG_MACH_SUN6I) 147 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 148 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 149 clock_twi_onoff(3, 1); 150 #elif defined(CONFIG_MACH_SUN7I) || \ 151 defined(CONFIG_MACH_SUN8I_R40) 152 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 153 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 154 clock_twi_onoff(3, 1); 155 #endif 156 #endif 157 158 #ifdef CONFIG_I2C4_ENABLE 159 #if defined(CONFIG_MACH_SUN7I) || \ 160 defined(CONFIG_MACH_SUN8I_R40) 161 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 162 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 163 clock_twi_onoff(4, 1); 164 #endif 165 #endif 166 167 #ifdef CONFIG_R_I2C_ENABLE 168 clock_twi_onoff(5, 1); 169 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 170 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 171 #endif 172 } 173 174 /* add board specific code here */ 175 int board_init(void) 176 { 177 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin; 178 179 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 180 181 #ifndef CONFIG_ARM64 182 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 183 debug("id_pfr1: 0x%08x\n", id_pfr1); 184 /* Generic Timer Extension available? */ 185 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 186 uint32_t freq; 187 188 debug("Setting CNTFRQ\n"); 189 190 /* 191 * CNTFRQ is a secure register, so we will crash if we try to 192 * write this from the non-secure world (read is OK, though). 193 * In case some bootcode has already set the correct value, 194 * we avoid the risk of writing to it. 195 */ 196 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 197 if (freq != COUNTER_FREQUENCY) { 198 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 199 freq, COUNTER_FREQUENCY); 200 #ifdef CONFIG_NON_SECURE 201 printf("arch timer frequency is wrong, but cannot adjust it\n"); 202 #else 203 asm volatile("mcr p15, 0, %0, c14, c0, 0" 204 : : "r"(COUNTER_FREQUENCY)); 205 #endif 206 } 207 } 208 #endif /* !CONFIG_ARM64 */ 209 210 ret = axp_gpio_init(); 211 if (ret) 212 return ret; 213 214 #ifdef CONFIG_SATAPWR 215 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR); 216 gpio_request(satapwr_pin, "satapwr"); 217 gpio_direction_output(satapwr_pin, 1); 218 #endif 219 #ifdef CONFIG_MACPWR 220 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR); 221 gpio_request(macpwr_pin, "macpwr"); 222 gpio_direction_output(macpwr_pin, 1); 223 #endif 224 225 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 226 return soft_i2c_board_init(); 227 } 228 229 int dram_init(void) 230 { 231 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 232 233 return 0; 234 } 235 236 #if defined(CONFIG_NAND_SUNXI) 237 static void nand_pinmux_setup(void) 238 { 239 unsigned int pin; 240 241 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 242 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 243 244 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 245 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 246 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 247 #endif 248 /* sun4i / sun7i do have a PC23, but it is not used for nand, 249 * only sun7i has a PC24 */ 250 #ifdef CONFIG_MACH_SUN7I 251 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 252 #endif 253 } 254 255 static void nand_clock_setup(void) 256 { 257 struct sunxi_ccm_reg *const ccm = 258 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 259 260 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 261 #ifdef CONFIG_MACH_SUN9I 262 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 263 #else 264 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 265 #endif 266 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 267 } 268 269 void board_nand_init(void) 270 { 271 nand_pinmux_setup(); 272 nand_clock_setup(); 273 #ifndef CONFIG_SPL_BUILD 274 sunxi_nand_init(); 275 #endif 276 } 277 #endif 278 279 #ifdef CONFIG_GENERIC_MMC 280 static void mmc_pinmux_setup(int sdc) 281 { 282 unsigned int pin; 283 __maybe_unused int pins; 284 285 switch (sdc) { 286 case 0: 287 /* SDC0: PF0-PF5 */ 288 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 289 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 290 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 291 sunxi_gpio_set_drv(pin, 2); 292 } 293 break; 294 295 case 1: 296 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 297 298 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 299 defined(CONFIG_MACH_SUN8I_R40) 300 if (pins == SUNXI_GPIO_H) { 301 /* SDC1: PH22-PH-27 */ 302 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 303 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 304 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 305 sunxi_gpio_set_drv(pin, 2); 306 } 307 } else { 308 /* SDC1: PG0-PG5 */ 309 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 310 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 311 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 312 sunxi_gpio_set_drv(pin, 2); 313 } 314 } 315 #elif defined(CONFIG_MACH_SUN5I) 316 /* SDC1: PG3-PG8 */ 317 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 318 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 319 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 320 sunxi_gpio_set_drv(pin, 2); 321 } 322 #elif defined(CONFIG_MACH_SUN6I) 323 /* SDC1: PG0-PG5 */ 324 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 325 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 326 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 327 sunxi_gpio_set_drv(pin, 2); 328 } 329 #elif defined(CONFIG_MACH_SUN8I) 330 if (pins == SUNXI_GPIO_D) { 331 /* SDC1: PD2-PD7 */ 332 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 333 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 334 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 335 sunxi_gpio_set_drv(pin, 2); 336 } 337 } else { 338 /* SDC1: PG0-PG5 */ 339 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 340 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 341 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 342 sunxi_gpio_set_drv(pin, 2); 343 } 344 } 345 #endif 346 break; 347 348 case 2: 349 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 350 351 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 352 /* SDC2: PC6-PC11 */ 353 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 354 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 355 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 356 sunxi_gpio_set_drv(pin, 2); 357 } 358 #elif defined(CONFIG_MACH_SUN5I) 359 if (pins == SUNXI_GPIO_E) { 360 /* SDC2: PE4-PE9 */ 361 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 362 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 363 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 364 sunxi_gpio_set_drv(pin, 2); 365 } 366 } else { 367 /* SDC2: PC6-PC15 */ 368 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 369 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 370 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 371 sunxi_gpio_set_drv(pin, 2); 372 } 373 } 374 #elif defined(CONFIG_MACH_SUN6I) 375 if (pins == SUNXI_GPIO_A) { 376 /* SDC2: PA9-PA14 */ 377 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 378 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 379 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 380 sunxi_gpio_set_drv(pin, 2); 381 } 382 } else { 383 /* SDC2: PC6-PC15, PC24 */ 384 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 385 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 386 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 387 sunxi_gpio_set_drv(pin, 2); 388 } 389 390 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 391 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 392 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 393 } 394 #elif defined(CONFIG_MACH_SUN8I_R40) 395 /* SDC2: PC6-PC15, PC24 */ 396 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 397 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 399 sunxi_gpio_set_drv(pin, 2); 400 } 401 402 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 403 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 404 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 405 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 406 /* SDC2: PC5-PC6, PC8-PC16 */ 407 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 408 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 409 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 410 sunxi_gpio_set_drv(pin, 2); 411 } 412 413 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 414 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 415 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 416 sunxi_gpio_set_drv(pin, 2); 417 } 418 #elif defined(CONFIG_MACH_SUN9I) 419 /* SDC2: PC6-PC16 */ 420 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) { 421 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 422 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 423 sunxi_gpio_set_drv(pin, 2); 424 } 425 #endif 426 break; 427 428 case 3: 429 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 430 431 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \ 432 defined(CONFIG_MACH_SUN8I_R40) 433 /* SDC3: PI4-PI9 */ 434 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 435 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 436 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 437 sunxi_gpio_set_drv(pin, 2); 438 } 439 #elif defined(CONFIG_MACH_SUN6I) 440 if (pins == SUNXI_GPIO_A) { 441 /* SDC3: PA9-PA14 */ 442 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 443 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 445 sunxi_gpio_set_drv(pin, 2); 446 } 447 } else { 448 /* SDC3: PC6-PC15, PC24 */ 449 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 450 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 451 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 452 sunxi_gpio_set_drv(pin, 2); 453 } 454 455 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 456 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 457 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 458 } 459 #endif 460 break; 461 462 default: 463 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 464 break; 465 } 466 } 467 468 int board_mmc_init(bd_t *bis) 469 { 470 __maybe_unused struct mmc *mmc0, *mmc1; 471 __maybe_unused char buf[512]; 472 473 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 474 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 475 if (!mmc0) 476 return -1; 477 478 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 479 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 480 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 481 if (!mmc1) 482 return -1; 483 #endif 484 485 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 486 /* 487 * On systems with an emmc (mmc2), figure out if we are booting from 488 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 489 * are searched there first. Note we only do this for u-boot proper, 490 * not for the SPL, see spl_boot_device(). 491 */ 492 if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { 493 /* Booting from emmc / mmc2, swap */ 494 mmc0->block_dev.devnum = 1; 495 mmc1->block_dev.devnum = 0; 496 } 497 #endif 498 499 return 0; 500 } 501 #endif 502 503 #ifdef CONFIG_SPL_BUILD 504 void sunxi_board_init(void) 505 { 506 int power_failed = 0; 507 unsigned long ramsize; 508 509 #ifdef CONFIG_SY8106A_POWER 510 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 511 #endif 512 513 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 514 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 515 defined CONFIG_AXP818_POWER 516 power_failed = axp_init(); 517 518 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 519 defined CONFIG_AXP818_POWER 520 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 521 #endif 522 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 523 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 524 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 525 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 526 #endif 527 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 528 defined CONFIG_AXP818_POWER 529 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 530 #endif 531 532 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 533 defined CONFIG_AXP818_POWER 534 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 535 #endif 536 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 537 #if !defined(CONFIG_AXP152_POWER) 538 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 539 #endif 540 #ifdef CONFIG_AXP209_POWER 541 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 542 #endif 543 544 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 545 defined(CONFIG_AXP818_POWER) 546 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 547 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 548 #if !defined CONFIG_AXP809_POWER 549 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 550 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 551 #endif 552 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 553 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 554 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 555 #endif 556 557 #ifdef CONFIG_AXP818_POWER 558 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 559 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 560 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 561 #endif 562 563 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 564 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 565 #endif 566 #endif 567 printf("DRAM:"); 568 ramsize = sunxi_dram_init(); 569 printf(" %d MiB\n", (int)(ramsize >> 20)); 570 if (!ramsize) 571 hang(); 572 573 /* 574 * Only clock up the CPU to full speed if we are reasonably 575 * assured it's being powered with suitable core voltage 576 */ 577 if (!power_failed) 578 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 579 else 580 printf("Failed to set core voltage! Can't set CPU frequency\n"); 581 } 582 #endif 583 584 #ifdef CONFIG_USB_GADGET 585 int g_dnl_board_usb_cable_connected(void) 586 { 587 return sunxi_usb_phy_vbus_detect(0); 588 } 589 #endif 590 591 #ifdef CONFIG_SERIAL_TAG 592 void get_board_serial(struct tag_serialnr *serialnr) 593 { 594 char *serial_string; 595 unsigned long long serial; 596 597 serial_string = getenv("serial#"); 598 599 if (serial_string) { 600 serial = simple_strtoull(serial_string, NULL, 16); 601 602 serialnr->high = (unsigned int) (serial >> 32); 603 serialnr->low = (unsigned int) (serial & 0xffffffff); 604 } else { 605 serialnr->high = 0; 606 serialnr->low = 0; 607 } 608 } 609 #endif 610 611 /* 612 * Check the SPL header for the "sunxi" variant. If found: parse values 613 * that might have been passed by the loader ("fel" utility), and update 614 * the environment accordingly. 615 */ 616 static void parse_spl_header(const uint32_t spl_addr) 617 { 618 struct boot_file_head *spl = (void *)(ulong)spl_addr; 619 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 620 return; /* signature mismatch, no usable header */ 621 622 uint8_t spl_header_version = spl->spl_signature[3]; 623 if (spl_header_version != SPL_HEADER_VERSION) { 624 printf("sunxi SPL version mismatch: expected %u, got %u\n", 625 SPL_HEADER_VERSION, spl_header_version); 626 return; 627 } 628 if (!spl->fel_script_address) 629 return; 630 631 if (spl->fel_uEnv_length != 0) { 632 /* 633 * data is expected in uEnv.txt compatible format, so "env 634 * import -t" the string(s) at fel_script_address right away. 635 */ 636 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address, 637 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 638 return; 639 } 640 /* otherwise assume .scr format (mkimage-type script) */ 641 setenv_hex("fel_scriptaddr", spl->fel_script_address); 642 } 643 644 /* 645 * Note this function gets called multiple times. 646 * It must not make any changes to env variables which already exist. 647 */ 648 static void setup_environment(const void *fdt) 649 { 650 char serial_string[17] = { 0 }; 651 unsigned int sid[4]; 652 uint8_t mac_addr[6]; 653 char ethaddr[16]; 654 int i, ret; 655 656 ret = sunxi_get_sid(sid); 657 if (ret == 0 && sid[0] != 0) { 658 /* 659 * The single words 1 - 3 of the SID have quite a few bits 660 * which are the same on many models, so we take a crc32 661 * of all 3 words, to get a more unique value. 662 * 663 * Note we only do this on newer SoCs as we cannot change 664 * the algorithm on older SoCs since those have been using 665 * fixed mac-addresses based on only using word 3 for a 666 * long time and changing a fixed mac-address with an 667 * u-boot update is not good. 668 */ 669 #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ 670 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ 671 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) 672 sid[3] = crc32(0, (unsigned char *)&sid[1], 12); 673 #endif 674 675 /* Ensure the NIC specific bytes of the mac are not all 0 */ 676 if ((sid[3] & 0xffffff) == 0) 677 sid[3] |= 0x800000; 678 679 for (i = 0; i < 4; i++) { 680 sprintf(ethaddr, "ethernet%d", i); 681 if (!fdt_get_alias(fdt, ethaddr)) 682 continue; 683 684 if (i == 0) 685 strcpy(ethaddr, "ethaddr"); 686 else 687 sprintf(ethaddr, "eth%daddr", i); 688 689 if (getenv(ethaddr)) 690 continue; 691 692 /* Non OUI / registered MAC address */ 693 mac_addr[0] = (i << 4) | 0x02; 694 mac_addr[1] = (sid[0] >> 0) & 0xff; 695 mac_addr[2] = (sid[3] >> 24) & 0xff; 696 mac_addr[3] = (sid[3] >> 16) & 0xff; 697 mac_addr[4] = (sid[3] >> 8) & 0xff; 698 mac_addr[5] = (sid[3] >> 0) & 0xff; 699 700 eth_setenv_enetaddr(ethaddr, mac_addr); 701 } 702 703 if (!getenv("serial#")) { 704 snprintf(serial_string, sizeof(serial_string), 705 "%08x%08x", sid[0], sid[3]); 706 707 setenv("serial#", serial_string); 708 } 709 } 710 } 711 712 int misc_init_r(void) 713 { 714 __maybe_unused int ret; 715 716 setenv("fel_booted", NULL); 717 setenv("fel_scriptaddr", NULL); 718 /* determine if we are running in FEL mode */ 719 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 720 setenv("fel_booted", "1"); 721 parse_spl_header(SPL_ADDR); 722 } 723 724 setup_environment(gd->fdt_blob); 725 726 #ifndef CONFIG_MACH_SUN9I 727 ret = sunxi_usb_phy_probe(); 728 if (ret) 729 return ret; 730 #endif 731 sunxi_musb_board_init(); 732 733 return 0; 734 } 735 736 int ft_board_setup(void *blob, bd_t *bd) 737 { 738 int __maybe_unused r; 739 740 /* 741 * Call setup_environment again in case the boot fdt has 742 * ethernet aliases the u-boot copy does not have. 743 */ 744 setup_environment(blob); 745 746 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 747 r = sunxi_simplefb_setup(blob); 748 if (r) 749 return r; 750 #endif 751 return 0; 752 } 753