1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usbc.h> 32 #include <asm/io.h> 33 #include <linux/usb/musb.h> 34 #include <net.h> 35 36 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 37 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 38 int soft_i2c_gpio_sda; 39 int soft_i2c_gpio_scl; 40 #endif 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* add board specific code here */ 45 int board_init(void) 46 { 47 int id_pfr1; 48 49 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 50 51 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 52 debug("id_pfr1: 0x%08x\n", id_pfr1); 53 /* Generic Timer Extension available? */ 54 if ((id_pfr1 >> 16) & 0xf) { 55 debug("Setting CNTFRQ\n"); 56 /* CNTFRQ == 24 MHz */ 57 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 58 } 59 60 return 0; 61 } 62 63 int dram_init(void) 64 { 65 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 66 67 return 0; 68 } 69 70 #ifdef CONFIG_GENERIC_MMC 71 static void mmc_pinmux_setup(int sdc) 72 { 73 unsigned int pin; 74 __maybe_unused int pins; 75 76 switch (sdc) { 77 case 0: 78 /* SDC0: PF0-PF5 */ 79 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 80 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 81 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 82 sunxi_gpio_set_drv(pin, 2); 83 } 84 break; 85 86 case 1: 87 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 88 89 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 90 if (pins == SUNXI_GPIO_H) { 91 /* SDC1: PH22-PH-27 */ 92 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 93 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 94 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 95 sunxi_gpio_set_drv(pin, 2); 96 } 97 } else { 98 /* SDC1: PG0-PG5 */ 99 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 100 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 101 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 102 sunxi_gpio_set_drv(pin, 2); 103 } 104 } 105 #elif defined(CONFIG_MACH_SUN5I) 106 /* SDC1: PG3-PG8 */ 107 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 108 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 109 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 110 sunxi_gpio_set_drv(pin, 2); 111 } 112 #elif defined(CONFIG_MACH_SUN6I) 113 /* SDC1: PG0-PG5 */ 114 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 115 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 116 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 117 sunxi_gpio_set_drv(pin, 2); 118 } 119 #elif defined(CONFIG_MACH_SUN8I) 120 if (pins == SUNXI_GPIO_D) { 121 /* SDC1: PD2-PD7 */ 122 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 123 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 124 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 125 sunxi_gpio_set_drv(pin, 2); 126 } 127 } else { 128 /* SDC1: PG0-PG5 */ 129 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 130 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 131 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 132 sunxi_gpio_set_drv(pin, 2); 133 } 134 } 135 #endif 136 break; 137 138 case 2: 139 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 140 141 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 142 /* SDC2: PC6-PC11 */ 143 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 144 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 145 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 146 sunxi_gpio_set_drv(pin, 2); 147 } 148 #elif defined(CONFIG_MACH_SUN5I) 149 if (pins == SUNXI_GPIO_E) { 150 /* SDC2: PE4-PE9 */ 151 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 152 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 153 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 154 sunxi_gpio_set_drv(pin, 2); 155 } 156 } else { 157 /* SDC2: PC6-PC15 */ 158 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 159 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 160 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 161 sunxi_gpio_set_drv(pin, 2); 162 } 163 } 164 #elif defined(CONFIG_MACH_SUN6I) 165 if (pins == SUNXI_GPIO_A) { 166 /* SDC2: PA9-PA14 */ 167 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 168 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 169 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 170 sunxi_gpio_set_drv(pin, 2); 171 } 172 } else { 173 /* SDC2: PC6-PC15, PC24 */ 174 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 175 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 176 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 177 sunxi_gpio_set_drv(pin, 2); 178 } 179 180 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 181 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 182 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 183 } 184 #elif defined(CONFIG_MACH_SUN8I) 185 /* SDC2: PC5-PC6, PC8-PC16 */ 186 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 187 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 188 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 189 sunxi_gpio_set_drv(pin, 2); 190 } 191 192 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 193 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 194 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 195 sunxi_gpio_set_drv(pin, 2); 196 } 197 #endif 198 break; 199 200 case 3: 201 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 202 203 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 204 /* SDC3: PI4-PI9 */ 205 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 206 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 207 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 208 sunxi_gpio_set_drv(pin, 2); 209 } 210 #elif defined(CONFIG_MACH_SUN6I) 211 if (pins == SUNXI_GPIO_A) { 212 /* SDC3: PA9-PA14 */ 213 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 214 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 215 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 216 sunxi_gpio_set_drv(pin, 2); 217 } 218 } else { 219 /* SDC3: PC6-PC15, PC24 */ 220 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 221 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 222 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 223 sunxi_gpio_set_drv(pin, 2); 224 } 225 226 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 227 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 228 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 229 } 230 #endif 231 break; 232 233 default: 234 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 235 break; 236 } 237 } 238 239 int board_mmc_init(bd_t *bis) 240 { 241 __maybe_unused struct mmc *mmc0, *mmc1; 242 __maybe_unused char buf[512]; 243 244 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 245 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 246 if (!mmc0) 247 return -1; 248 249 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 250 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 251 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 252 if (!mmc1) 253 return -1; 254 #endif 255 256 #if CONFIG_MMC_SUNXI_SLOT == 0 && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 257 /* 258 * Both mmc0 and mmc2 are bootable, figure out where we're booting 259 * from. Try mmc0 first, just like the brom does. 260 */ 261 if (mmc_getcd(mmc0) && mmc_init(mmc0) == 0 && 262 mmc0->block_dev.block_read(0, 16, 1, buf) == 1) { 263 buf[12] = 0; 264 if (strcmp(&buf[4], "eGON.BT0") == 0) 265 return 0; 266 } 267 268 /* no bootable card in mmc0, so we must be booting from mmc2, swap */ 269 mmc0->block_dev.dev = 1; 270 mmc1->block_dev.dev = 0; 271 #endif 272 273 return 0; 274 } 275 #endif 276 277 void i2c_init_board(void) 278 { 279 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB_TWI0); 280 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB_TWI0); 281 clock_twi_onoff(0, 1); 282 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 283 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 284 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 285 #endif 286 } 287 288 #ifdef CONFIG_SPL_BUILD 289 void sunxi_board_init(void) 290 { 291 int power_failed = 0; 292 unsigned long ramsize; 293 294 #ifdef CONFIG_AXP152_POWER 295 power_failed = axp152_init(); 296 power_failed |= axp152_set_dcdc2(1400); 297 power_failed |= axp152_set_dcdc3(1500); 298 power_failed |= axp152_set_dcdc4(1250); 299 power_failed |= axp152_set_ldo2(3000); 300 #endif 301 #ifdef CONFIG_AXP209_POWER 302 power_failed |= axp209_init(); 303 power_failed |= axp209_set_dcdc2(1400); 304 power_failed |= axp209_set_dcdc3(1250); 305 power_failed |= axp209_set_ldo2(3000); 306 power_failed |= axp209_set_ldo3(2800); 307 power_failed |= axp209_set_ldo4(2800); 308 #endif 309 #ifdef CONFIG_AXP221_POWER 310 power_failed = axp221_init(); 311 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 312 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 313 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 314 #ifdef CONFIG_MACH_SUN6I 315 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 316 #else 317 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 318 #endif 319 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 320 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 321 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 322 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 323 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 324 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 325 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 326 #endif 327 328 printf("DRAM:"); 329 ramsize = sunxi_dram_init(); 330 printf(" %lu MiB\n", ramsize >> 20); 331 if (!ramsize) 332 hang(); 333 334 /* 335 * Only clock up the CPU to full speed if we are reasonably 336 * assured it's being powered with suitable core voltage 337 */ 338 if (!power_failed) 339 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 340 else 341 printf("Failed to set core voltage! Can't set CPU frequency\n"); 342 } 343 #endif 344 345 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 346 static struct musb_hdrc_config musb_config = { 347 .multipoint = 1, 348 .dyn_fifo = 1, 349 .num_eps = 6, 350 .ram_bits = 11, 351 }; 352 353 static struct musb_hdrc_platform_data musb_plat = { 354 #if defined(CONFIG_MUSB_HOST) 355 .mode = MUSB_HOST, 356 #else 357 .mode = MUSB_PERIPHERAL, 358 #endif 359 .config = &musb_config, 360 .power = 250, 361 .platform_ops = &sunxi_musb_ops, 362 }; 363 #endif 364 365 #ifdef CONFIG_USB_GADGET 366 int g_dnl_board_usb_cable_connected(void) 367 { 368 return sunxi_usbc_vbus_detect(0); 369 } 370 #endif 371 372 #ifdef CONFIG_MISC_INIT_R 373 int misc_init_r(void) 374 { 375 unsigned int sid[4]; 376 377 if (!getenv("ethaddr") && sunxi_get_sid(sid) == 0 && 378 sid[0] != 0 && sid[3] != 0) { 379 uint8_t mac_addr[6]; 380 381 mac_addr[0] = 0x02; /* Non OUI / registered MAC address */ 382 mac_addr[1] = (sid[0] >> 0) & 0xff; 383 mac_addr[2] = (sid[3] >> 24) & 0xff; 384 mac_addr[3] = (sid[3] >> 16) & 0xff; 385 mac_addr[4] = (sid[3] >> 8) & 0xff; 386 mac_addr[5] = (sid[3] >> 0) & 0xff; 387 388 eth_setenv_enetaddr("ethaddr", mac_addr); 389 } 390 391 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 392 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); 393 #endif 394 return 0; 395 } 396 #endif 397 398 #ifdef CONFIG_OF_BOARD_SETUP 399 int ft_board_setup(void *blob, bd_t *bd) 400 { 401 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 402 return sunxi_simplefb_setup(blob); 403 #endif 404 } 405 #endif /* CONFIG_OF_BOARD_SETUP */ 406