1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #include <axp_pmic.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/display.h> 20 #include <asm/arch/dram.h> 21 #include <asm/arch/gpio.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/spl.h> 24 #include <asm/arch/usb_phy.h> 25 #ifndef CONFIG_ARM64 26 #include <asm/armv7.h> 27 #endif 28 #include <asm/gpio.h> 29 #include <asm/io.h> 30 #include <environment.h> 31 #include <libfdt.h> 32 #include <nand.h> 33 #include <net.h> 34 #include <sy8106a.h> 35 36 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 37 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 38 int soft_i2c_gpio_sda; 39 int soft_i2c_gpio_scl; 40 41 static int soft_i2c_board_init(void) 42 { 43 int ret; 44 45 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 46 if (soft_i2c_gpio_sda < 0) { 47 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 48 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 49 return soft_i2c_gpio_sda; 50 } 51 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 52 if (ret) { 53 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 54 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 55 return ret; 56 } 57 58 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 59 if (soft_i2c_gpio_scl < 0) { 60 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 61 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 62 return soft_i2c_gpio_scl; 63 } 64 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 65 if (ret) { 66 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 67 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 68 return ret; 69 } 70 71 return 0; 72 } 73 #else 74 static int soft_i2c_board_init(void) { return 0; } 75 #endif 76 77 DECLARE_GLOBAL_DATA_PTR; 78 79 /* add board specific code here */ 80 int board_init(void) 81 { 82 __maybe_unused int id_pfr1, ret; 83 84 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 85 86 #ifndef CONFIG_ARM64 87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 88 debug("id_pfr1: 0x%08x\n", id_pfr1); 89 /* Generic Timer Extension available? */ 90 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) { 91 uint32_t freq; 92 93 debug("Setting CNTFRQ\n"); 94 95 /* 96 * CNTFRQ is a secure register, so we will crash if we try to 97 * write this from the non-secure world (read is OK, though). 98 * In case some bootcode has already set the correct value, 99 * we avoid the risk of writing to it. 100 */ 101 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq)); 102 if (freq != CONFIG_TIMER_CLK_FREQ) { 103 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n", 104 freq, CONFIG_TIMER_CLK_FREQ); 105 #ifdef CONFIG_NON_SECURE 106 printf("arch timer frequency is wrong, but cannot adjust it\n"); 107 #else 108 asm volatile("mcr p15, 0, %0, c14, c0, 0" 109 : : "r"(CONFIG_TIMER_CLK_FREQ)); 110 #endif 111 } 112 } 113 #endif /* !CONFIG_ARM64 */ 114 115 ret = axp_gpio_init(); 116 if (ret) 117 return ret; 118 119 #ifdef CONFIG_SATAPWR 120 gpio_request(CONFIG_SATAPWR, "satapwr"); 121 gpio_direction_output(CONFIG_SATAPWR, 1); 122 #endif 123 #ifdef CONFIG_MACPWR 124 gpio_request(CONFIG_MACPWR, "macpwr"); 125 gpio_direction_output(CONFIG_MACPWR, 1); 126 #endif 127 128 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 129 return soft_i2c_board_init(); 130 } 131 132 int dram_init(void) 133 { 134 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 135 136 return 0; 137 } 138 139 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 140 static void nand_pinmux_setup(void) 141 { 142 unsigned int pin; 143 144 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) 145 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 146 147 #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I 148 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) 149 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 150 #endif 151 /* sun4i / sun7i do have a PC23, but it is not used for nand, 152 * only sun7i has a PC24 */ 153 #ifdef CONFIG_MACH_SUN7I 154 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 155 #endif 156 } 157 158 static void nand_clock_setup(void) 159 { 160 struct sunxi_ccm_reg *const ccm = 161 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 162 163 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 164 #ifdef CONFIG_MACH_SUN9I 165 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 166 #else 167 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 168 #endif 169 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 170 } 171 172 void board_nand_init(void) 173 { 174 nand_pinmux_setup(); 175 nand_clock_setup(); 176 } 177 #endif 178 179 #ifdef CONFIG_GENERIC_MMC 180 static void mmc_pinmux_setup(int sdc) 181 { 182 unsigned int pin; 183 __maybe_unused int pins; 184 185 switch (sdc) { 186 case 0: 187 /* SDC0: PF0-PF5 */ 188 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 189 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 190 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 191 sunxi_gpio_set_drv(pin, 2); 192 } 193 break; 194 195 case 1: 196 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 197 198 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 199 if (pins == SUNXI_GPIO_H) { 200 /* SDC1: PH22-PH-27 */ 201 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 202 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 203 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 204 sunxi_gpio_set_drv(pin, 2); 205 } 206 } else { 207 /* SDC1: PG0-PG5 */ 208 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 209 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 210 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 211 sunxi_gpio_set_drv(pin, 2); 212 } 213 } 214 #elif defined(CONFIG_MACH_SUN5I) 215 /* SDC1: PG3-PG8 */ 216 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 217 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 218 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 219 sunxi_gpio_set_drv(pin, 2); 220 } 221 #elif defined(CONFIG_MACH_SUN6I) 222 /* SDC1: PG0-PG5 */ 223 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 224 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 225 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 226 sunxi_gpio_set_drv(pin, 2); 227 } 228 #elif defined(CONFIG_MACH_SUN8I) 229 if (pins == SUNXI_GPIO_D) { 230 /* SDC1: PD2-PD7 */ 231 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 232 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 233 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 234 sunxi_gpio_set_drv(pin, 2); 235 } 236 } else { 237 /* SDC1: PG0-PG5 */ 238 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 239 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 240 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 241 sunxi_gpio_set_drv(pin, 2); 242 } 243 } 244 #endif 245 break; 246 247 case 2: 248 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 249 250 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 251 /* SDC2: PC6-PC11 */ 252 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 253 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 254 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 255 sunxi_gpio_set_drv(pin, 2); 256 } 257 #elif defined(CONFIG_MACH_SUN5I) 258 if (pins == SUNXI_GPIO_E) { 259 /* SDC2: PE4-PE9 */ 260 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 261 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 262 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 263 sunxi_gpio_set_drv(pin, 2); 264 } 265 } else { 266 /* SDC2: PC6-PC15 */ 267 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 268 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 269 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 270 sunxi_gpio_set_drv(pin, 2); 271 } 272 } 273 #elif defined(CONFIG_MACH_SUN6I) 274 if (pins == SUNXI_GPIO_A) { 275 /* SDC2: PA9-PA14 */ 276 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 277 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 278 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 279 sunxi_gpio_set_drv(pin, 2); 280 } 281 } else { 282 /* SDC2: PC6-PC15, PC24 */ 283 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 284 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 285 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 286 sunxi_gpio_set_drv(pin, 2); 287 } 288 289 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 290 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 291 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 292 } 293 #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I) 294 /* SDC2: PC5-PC6, PC8-PC16 */ 295 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 296 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 297 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 298 sunxi_gpio_set_drv(pin, 2); 299 } 300 301 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 302 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 303 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 304 sunxi_gpio_set_drv(pin, 2); 305 } 306 #endif 307 break; 308 309 case 3: 310 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 311 312 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 313 /* SDC3: PI4-PI9 */ 314 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 315 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 316 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 317 sunxi_gpio_set_drv(pin, 2); 318 } 319 #elif defined(CONFIG_MACH_SUN6I) 320 if (pins == SUNXI_GPIO_A) { 321 /* SDC3: PA9-PA14 */ 322 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 323 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 324 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 325 sunxi_gpio_set_drv(pin, 2); 326 } 327 } else { 328 /* SDC3: PC6-PC15, PC24 */ 329 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 330 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 331 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 332 sunxi_gpio_set_drv(pin, 2); 333 } 334 335 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 336 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 337 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 338 } 339 #endif 340 break; 341 342 default: 343 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 344 break; 345 } 346 } 347 348 int board_mmc_init(bd_t *bis) 349 { 350 __maybe_unused struct mmc *mmc0, *mmc1; 351 __maybe_unused char buf[512]; 352 353 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 354 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 355 if (!mmc0) 356 return -1; 357 358 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 359 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 360 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 361 if (!mmc1) 362 return -1; 363 #endif 364 365 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 366 /* 367 * On systems with an emmc (mmc2), figure out if we are booting from 368 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 369 * are searched there first. Note we only do this for u-boot proper, 370 * not for the SPL, see spl_boot_device(). 371 */ 372 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 373 sunxi_mmc_has_egon_boot_signature(mmc1)) { 374 /* Booting from emmc / mmc2, swap */ 375 mmc0->block_dev.devnum = 1; 376 mmc1->block_dev.devnum = 0; 377 } 378 #endif 379 380 return 0; 381 } 382 #endif 383 384 void i2c_init_board(void) 385 { 386 #ifdef CONFIG_I2C0_ENABLE 387 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 388 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 389 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 390 clock_twi_onoff(0, 1); 391 #elif defined(CONFIG_MACH_SUN6I) 392 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 393 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 394 clock_twi_onoff(0, 1); 395 #elif defined(CONFIG_MACH_SUN8I) 396 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 397 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 398 clock_twi_onoff(0, 1); 399 #endif 400 #endif 401 402 #ifdef CONFIG_I2C1_ENABLE 403 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 404 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 405 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 406 clock_twi_onoff(1, 1); 407 #elif defined(CONFIG_MACH_SUN5I) 408 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 409 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 410 clock_twi_onoff(1, 1); 411 #elif defined(CONFIG_MACH_SUN6I) 412 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 413 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 414 clock_twi_onoff(1, 1); 415 #elif defined(CONFIG_MACH_SUN8I) 416 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 417 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 418 clock_twi_onoff(1, 1); 419 #endif 420 #endif 421 422 #ifdef CONFIG_I2C2_ENABLE 423 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 424 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 425 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 426 clock_twi_onoff(2, 1); 427 #elif defined(CONFIG_MACH_SUN5I) 428 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 429 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 430 clock_twi_onoff(2, 1); 431 #elif defined(CONFIG_MACH_SUN6I) 432 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 433 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 434 clock_twi_onoff(2, 1); 435 #elif defined(CONFIG_MACH_SUN8I) 436 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 437 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 438 clock_twi_onoff(2, 1); 439 #endif 440 #endif 441 442 #ifdef CONFIG_I2C3_ENABLE 443 #if defined(CONFIG_MACH_SUN6I) 444 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 445 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 446 clock_twi_onoff(3, 1); 447 #elif defined(CONFIG_MACH_SUN7I) 448 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 449 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 450 clock_twi_onoff(3, 1); 451 #endif 452 #endif 453 454 #ifdef CONFIG_I2C4_ENABLE 455 #if defined(CONFIG_MACH_SUN7I) 456 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 457 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 458 clock_twi_onoff(4, 1); 459 #endif 460 #endif 461 462 #ifdef CONFIG_R_I2C_ENABLE 463 clock_twi_onoff(5, 1); 464 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI); 465 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI); 466 #endif 467 } 468 469 #ifdef CONFIG_SPL_BUILD 470 void sunxi_board_init(void) 471 { 472 int power_failed = 0; 473 unsigned long ramsize; 474 475 #ifdef CONFIG_SY8106A_POWER 476 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT); 477 #endif 478 479 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ 480 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 481 defined CONFIG_AXP818_POWER 482 power_failed = axp_init(); 483 484 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 485 defined CONFIG_AXP818_POWER 486 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); 487 #endif 488 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT); 489 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT); 490 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER) 491 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT); 492 #endif 493 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 494 defined CONFIG_AXP818_POWER 495 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT); 496 #endif 497 498 #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ 499 defined CONFIG_AXP818_POWER 500 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT); 501 #endif 502 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT); 503 #if !defined(CONFIG_AXP152_POWER) 504 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT); 505 #endif 506 #ifdef CONFIG_AXP209_POWER 507 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT); 508 #endif 509 510 #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \ 511 defined(CONFIG_AXP818_POWER) 512 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT); 513 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT); 514 #if !defined CONFIG_AXP809_POWER 515 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT); 516 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT); 517 #endif 518 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT); 519 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT); 520 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT); 521 #endif 522 523 #ifdef CONFIG_AXP818_POWER 524 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT); 525 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT); 526 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT); 527 #endif 528 529 #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER 530 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); 531 #endif 532 #endif 533 printf("DRAM:"); 534 ramsize = sunxi_dram_init(); 535 printf(" %d MiB\n", (int)(ramsize >> 20)); 536 if (!ramsize) 537 hang(); 538 539 /* 540 * Only clock up the CPU to full speed if we are reasonably 541 * assured it's being powered with suitable core voltage 542 */ 543 if (!power_failed) 544 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 545 else 546 printf("Failed to set core voltage! Can't set CPU frequency\n"); 547 } 548 #endif 549 550 #ifdef CONFIG_USB_GADGET 551 int g_dnl_board_usb_cable_connected(void) 552 { 553 return sunxi_usb_phy_vbus_detect(0); 554 } 555 #endif 556 557 #ifdef CONFIG_SERIAL_TAG 558 void get_board_serial(struct tag_serialnr *serialnr) 559 { 560 char *serial_string; 561 unsigned long long serial; 562 563 serial_string = getenv("serial#"); 564 565 if (serial_string) { 566 serial = simple_strtoull(serial_string, NULL, 16); 567 568 serialnr->high = (unsigned int) (serial >> 32); 569 serialnr->low = (unsigned int) (serial & 0xffffffff); 570 } else { 571 serialnr->high = 0; 572 serialnr->low = 0; 573 } 574 } 575 #endif 576 577 /* 578 * Check the SPL header for the "sunxi" variant. If found: parse values 579 * that might have been passed by the loader ("fel" utility), and update 580 * the environment accordingly. 581 */ 582 static void parse_spl_header(const uint32_t spl_addr) 583 { 584 struct boot_file_head *spl = (void *)(ulong)spl_addr; 585 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) 586 return; /* signature mismatch, no usable header */ 587 588 uint8_t spl_header_version = spl->spl_signature[3]; 589 if (spl_header_version != SPL_HEADER_VERSION) { 590 printf("sunxi SPL version mismatch: expected %u, got %u\n", 591 SPL_HEADER_VERSION, spl_header_version); 592 return; 593 } 594 if (!spl->fel_script_address) 595 return; 596 597 if (spl->fel_uEnv_length != 0) { 598 /* 599 * data is expected in uEnv.txt compatible format, so "env 600 * import -t" the string(s) at fel_script_address right away. 601 */ 602 himport_r(&env_htab, (char *)spl->fel_script_address, 603 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); 604 return; 605 } 606 /* otherwise assume .scr format (mkimage-type script) */ 607 setenv_hex("fel_scriptaddr", spl->fel_script_address); 608 } 609 610 /* 611 * Note this function gets called multiple times. 612 * It must not make any changes to env variables which already exist. 613 */ 614 static void setup_environment(const void *fdt) 615 { 616 char serial_string[17] = { 0 }; 617 unsigned int sid[4]; 618 uint8_t mac_addr[6]; 619 char ethaddr[16]; 620 int i, ret; 621 622 ret = sunxi_get_sid(sid); 623 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 624 for (i = 0; i < 4; i++) { 625 sprintf(ethaddr, "ethernet%d", i); 626 if (!fdt_get_alias(fdt, ethaddr)) 627 continue; 628 629 if (i == 0) 630 strcpy(ethaddr, "ethaddr"); 631 else 632 sprintf(ethaddr, "eth%daddr", i); 633 634 if (getenv(ethaddr)) 635 continue; 636 637 /* Non OUI / registered MAC address */ 638 mac_addr[0] = (i << 4) | 0x02; 639 mac_addr[1] = (sid[0] >> 0) & 0xff; 640 mac_addr[2] = (sid[3] >> 24) & 0xff; 641 mac_addr[3] = (sid[3] >> 16) & 0xff; 642 mac_addr[4] = (sid[3] >> 8) & 0xff; 643 mac_addr[5] = (sid[3] >> 0) & 0xff; 644 645 eth_setenv_enetaddr(ethaddr, mac_addr); 646 } 647 648 if (!getenv("serial#")) { 649 snprintf(serial_string, sizeof(serial_string), 650 "%08x%08x", sid[0], sid[3]); 651 652 setenv("serial#", serial_string); 653 } 654 } 655 } 656 657 int misc_init_r(void) 658 { 659 __maybe_unused int ret; 660 661 setenv("fel_booted", NULL); 662 setenv("fel_scriptaddr", NULL); 663 /* determine if we are running in FEL mode */ 664 if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ 665 setenv("fel_booted", "1"); 666 parse_spl_header(SPL_ADDR); 667 } 668 669 setup_environment(gd->fdt_blob); 670 671 #ifndef CONFIG_MACH_SUN9I 672 ret = sunxi_usb_phy_probe(); 673 if (ret) 674 return ret; 675 #endif 676 sunxi_musb_board_init(); 677 678 return 0; 679 } 680 681 int ft_board_setup(void *blob, bd_t *bd) 682 { 683 int __maybe_unused r; 684 685 /* 686 * Call setup_environment again in case the boot fdt has 687 * ethernet aliases the u-boot copy does not have. 688 */ 689 setup_environment(blob); 690 691 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 692 r = sunxi_simplefb_setup(blob); 693 if (r) 694 return r; 695 #endif 696 return 0; 697 } 698