1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usb_phy.h> 32 #include <asm/gpio.h> 33 #include <asm/io.h> 34 #include <linux/usb/musb.h> 35 #include <net.h> 36 37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 39 int soft_i2c_gpio_sda; 40 int soft_i2c_gpio_scl; 41 42 static int soft_i2c_board_init(void) 43 { 44 int ret; 45 46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 47 if (soft_i2c_gpio_sda < 0) { 48 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 50 return soft_i2c_gpio_sda; 51 } 52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 53 if (ret) { 54 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 56 return ret; 57 } 58 59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 60 if (soft_i2c_gpio_scl < 0) { 61 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 63 return soft_i2c_gpio_scl; 64 } 65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 66 if (ret) { 67 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 69 return ret; 70 } 71 72 return 0; 73 } 74 #else 75 static int soft_i2c_board_init(void) { return 0; } 76 #endif 77 78 DECLARE_GLOBAL_DATA_PTR; 79 80 /* add board specific code here */ 81 int board_init(void) 82 { 83 int id_pfr1, ret; 84 85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 86 87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 88 debug("id_pfr1: 0x%08x\n", id_pfr1); 89 /* Generic Timer Extension available? */ 90 if ((id_pfr1 >> 16) & 0xf) { 91 debug("Setting CNTFRQ\n"); 92 /* CNTFRQ == 24 MHz */ 93 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 94 } 95 96 ret = axp_gpio_init(); 97 if (ret) 98 return ret; 99 100 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 101 return soft_i2c_board_init(); 102 } 103 104 int dram_init(void) 105 { 106 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 107 108 return 0; 109 } 110 111 #ifdef CONFIG_GENERIC_MMC 112 static void mmc_pinmux_setup(int sdc) 113 { 114 unsigned int pin; 115 __maybe_unused int pins; 116 117 switch (sdc) { 118 case 0: 119 /* SDC0: PF0-PF5 */ 120 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 121 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 122 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 123 sunxi_gpio_set_drv(pin, 2); 124 } 125 break; 126 127 case 1: 128 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 129 130 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 131 if (pins == SUNXI_GPIO_H) { 132 /* SDC1: PH22-PH-27 */ 133 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 134 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 135 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 136 sunxi_gpio_set_drv(pin, 2); 137 } 138 } else { 139 /* SDC1: PG0-PG5 */ 140 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 141 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 142 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 143 sunxi_gpio_set_drv(pin, 2); 144 } 145 } 146 #elif defined(CONFIG_MACH_SUN5I) 147 /* SDC1: PG3-PG8 */ 148 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 149 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 150 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 151 sunxi_gpio_set_drv(pin, 2); 152 } 153 #elif defined(CONFIG_MACH_SUN6I) 154 /* SDC1: PG0-PG5 */ 155 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 156 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 157 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 158 sunxi_gpio_set_drv(pin, 2); 159 } 160 #elif defined(CONFIG_MACH_SUN8I) 161 if (pins == SUNXI_GPIO_D) { 162 /* SDC1: PD2-PD7 */ 163 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 164 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 165 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 166 sunxi_gpio_set_drv(pin, 2); 167 } 168 } else { 169 /* SDC1: PG0-PG5 */ 170 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 171 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 172 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 173 sunxi_gpio_set_drv(pin, 2); 174 } 175 } 176 #endif 177 break; 178 179 case 2: 180 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 181 182 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 183 /* SDC2: PC6-PC11 */ 184 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 185 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 186 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 187 sunxi_gpio_set_drv(pin, 2); 188 } 189 #elif defined(CONFIG_MACH_SUN5I) 190 if (pins == SUNXI_GPIO_E) { 191 /* SDC2: PE4-PE9 */ 192 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 193 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 194 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 195 sunxi_gpio_set_drv(pin, 2); 196 } 197 } else { 198 /* SDC2: PC6-PC15 */ 199 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 200 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 201 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 202 sunxi_gpio_set_drv(pin, 2); 203 } 204 } 205 #elif defined(CONFIG_MACH_SUN6I) 206 if (pins == SUNXI_GPIO_A) { 207 /* SDC2: PA9-PA14 */ 208 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 209 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 210 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 211 sunxi_gpio_set_drv(pin, 2); 212 } 213 } else { 214 /* SDC2: PC6-PC15, PC24 */ 215 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 216 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 217 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 218 sunxi_gpio_set_drv(pin, 2); 219 } 220 221 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 222 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 223 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 224 } 225 #elif defined(CONFIG_MACH_SUN8I) 226 /* SDC2: PC5-PC6, PC8-PC16 */ 227 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 228 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 229 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 230 sunxi_gpio_set_drv(pin, 2); 231 } 232 233 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 234 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 235 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 236 sunxi_gpio_set_drv(pin, 2); 237 } 238 #endif 239 break; 240 241 case 3: 242 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 243 244 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 245 /* SDC3: PI4-PI9 */ 246 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 247 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 248 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 249 sunxi_gpio_set_drv(pin, 2); 250 } 251 #elif defined(CONFIG_MACH_SUN6I) 252 if (pins == SUNXI_GPIO_A) { 253 /* SDC3: PA9-PA14 */ 254 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 255 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 256 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 257 sunxi_gpio_set_drv(pin, 2); 258 } 259 } else { 260 /* SDC3: PC6-PC15, PC24 */ 261 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 262 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 263 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 264 sunxi_gpio_set_drv(pin, 2); 265 } 266 267 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 268 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 269 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 270 } 271 #endif 272 break; 273 274 default: 275 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 276 break; 277 } 278 } 279 280 int board_mmc_init(bd_t *bis) 281 { 282 __maybe_unused struct mmc *mmc0, *mmc1; 283 __maybe_unused char buf[512]; 284 285 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 286 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 287 if (!mmc0) 288 return -1; 289 290 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 291 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 292 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 293 if (!mmc1) 294 return -1; 295 #endif 296 297 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 298 /* 299 * On systems with an emmc (mmc2), figure out if we are booting from 300 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 301 * are searched there first. Note we only do this for u-boot proper, 302 * not for the SPL, see spl_boot_device(). 303 */ 304 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 305 sunxi_mmc_has_egon_boot_signature(mmc1)) { 306 /* Booting from emmc / mmc2, swap */ 307 mmc0->block_dev.dev = 1; 308 mmc1->block_dev.dev = 0; 309 } 310 #endif 311 312 return 0; 313 } 314 #endif 315 316 void i2c_init_board(void) 317 { 318 #ifdef CONFIG_I2C0_ENABLE 319 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 320 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 321 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 322 clock_twi_onoff(0, 1); 323 #elif defined(CONFIG_MACH_SUN6I) 324 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 325 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 326 clock_twi_onoff(0, 1); 327 #elif defined(CONFIG_MACH_SUN8I) 328 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 329 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 330 clock_twi_onoff(0, 1); 331 #endif 332 #endif 333 334 #ifdef CONFIG_I2C1_ENABLE 335 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 336 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 337 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 338 clock_twi_onoff(1, 1); 339 #elif defined(CONFIG_MACH_SUN5I) 340 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 341 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 342 clock_twi_onoff(1, 1); 343 #elif defined(CONFIG_MACH_SUN6I) 344 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 345 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 346 clock_twi_onoff(1, 1); 347 #elif defined(CONFIG_MACH_SUN8I) 348 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 349 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 350 clock_twi_onoff(1, 1); 351 #endif 352 #endif 353 354 #ifdef CONFIG_I2C2_ENABLE 355 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 356 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 357 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 358 clock_twi_onoff(2, 1); 359 #elif defined(CONFIG_MACH_SUN5I) 360 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 361 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 362 clock_twi_onoff(2, 1); 363 #elif defined(CONFIG_MACH_SUN6I) 364 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 365 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 366 clock_twi_onoff(2, 1); 367 #elif defined(CONFIG_MACH_SUN8I) 368 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 369 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 370 clock_twi_onoff(2, 1); 371 #endif 372 #endif 373 374 #ifdef CONFIG_I2C3_ENABLE 375 #if defined(CONFIG_MACH_SUN6I) 376 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 377 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 378 clock_twi_onoff(3, 1); 379 #elif defined(CONFIG_MACH_SUN7I) 380 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 381 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 382 clock_twi_onoff(3, 1); 383 #endif 384 #endif 385 386 #ifdef CONFIG_I2C4_ENABLE 387 #if defined(CONFIG_MACH_SUN7I) 388 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 389 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 390 clock_twi_onoff(4, 1); 391 #endif 392 #endif 393 } 394 395 #ifdef CONFIG_SPL_BUILD 396 void sunxi_board_init(void) 397 { 398 int power_failed = 0; 399 unsigned long ramsize; 400 401 #ifdef CONFIG_AXP152_POWER 402 power_failed = axp152_init(); 403 power_failed |= axp152_set_dcdc2(1400); 404 power_failed |= axp152_set_dcdc3(1500); 405 power_failed |= axp152_set_dcdc4(1250); 406 power_failed |= axp152_set_ldo2(3000); 407 #endif 408 #ifdef CONFIG_AXP209_POWER 409 power_failed |= axp209_init(); 410 power_failed |= axp209_set_dcdc2(1400); 411 power_failed |= axp209_set_dcdc3(1250); 412 power_failed |= axp209_set_ldo2(3000); 413 power_failed |= axp209_set_ldo3(2800); 414 power_failed |= axp209_set_ldo4(2800); 415 #endif 416 #ifdef CONFIG_AXP221_POWER 417 power_failed = axp221_init(); 418 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 419 power_failed |= axp221_set_dcdc2(1200); /* A31:VDD-GPU, A23:VDD-SYS */ 420 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 421 #ifdef CONFIG_MACH_SUN6I 422 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 423 #else 424 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 425 #endif 426 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 427 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 428 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 429 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 430 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 431 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 432 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 433 #endif 434 435 printf("DRAM:"); 436 ramsize = sunxi_dram_init(); 437 printf(" %lu MiB\n", ramsize >> 20); 438 if (!ramsize) 439 hang(); 440 441 /* 442 * Only clock up the CPU to full speed if we are reasonably 443 * assured it's being powered with suitable core voltage 444 */ 445 if (!power_failed) 446 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 447 else 448 printf("Failed to set core voltage! Can't set CPU frequency\n"); 449 } 450 #endif 451 452 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 453 extern const struct musb_platform_ops sunxi_musb_ops; 454 455 static struct musb_hdrc_config musb_config = { 456 .multipoint = 1, 457 .dyn_fifo = 1, 458 .num_eps = 6, 459 .ram_bits = 11, 460 }; 461 462 static struct musb_hdrc_platform_data musb_plat = { 463 #if defined(CONFIG_MUSB_HOST) 464 .mode = MUSB_HOST, 465 #else 466 .mode = MUSB_PERIPHERAL, 467 #endif 468 .config = &musb_config, 469 .power = 250, 470 .platform_ops = &sunxi_musb_ops, 471 }; 472 #endif 473 474 #ifdef CONFIG_USB_GADGET 475 int g_dnl_board_usb_cable_connected(void) 476 { 477 return sunxi_usb_phy_vbus_detect(0); 478 } 479 #endif 480 481 #ifdef CONFIG_SERIAL_TAG 482 void get_board_serial(struct tag_serialnr *serialnr) 483 { 484 char *serial_string; 485 unsigned long long serial; 486 487 serial_string = getenv("serial#"); 488 489 if (serial_string) { 490 serial = simple_strtoull(serial_string, NULL, 16); 491 492 serialnr->high = (unsigned int) (serial >> 32); 493 serialnr->low = (unsigned int) (serial & 0xffffffff); 494 } else { 495 serialnr->high = 0; 496 serialnr->low = 0; 497 } 498 } 499 #endif 500 501 #ifdef CONFIG_MISC_INIT_R 502 int misc_init_r(void) 503 { 504 char serial_string[17] = { 0 }; 505 unsigned int sid[4]; 506 uint8_t mac_addr[6]; 507 int ret; 508 509 ret = sunxi_get_sid(sid); 510 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 511 if (!getenv("ethaddr")) { 512 /* Non OUI / registered MAC address */ 513 mac_addr[0] = 0x02; 514 mac_addr[1] = (sid[0] >> 0) & 0xff; 515 mac_addr[2] = (sid[3] >> 24) & 0xff; 516 mac_addr[3] = (sid[3] >> 16) & 0xff; 517 mac_addr[4] = (sid[3] >> 8) & 0xff; 518 mac_addr[5] = (sid[3] >> 0) & 0xff; 519 520 eth_setenv_enetaddr("ethaddr", mac_addr); 521 } 522 523 if (!getenv("serial#")) { 524 snprintf(serial_string, sizeof(serial_string), 525 "%08x%08x", sid[0], sid[3]); 526 527 setenv("serial#", serial_string); 528 } 529 } 530 531 #ifndef CONFIG_MACH_SUN9I 532 ret = sunxi_usb_phy_probe(); 533 if (ret) 534 return ret; 535 #endif 536 #if defined(CONFIG_MUSB_HOST) || defined(CONFIG_MUSB_GADGET) 537 musb_register(&musb_plat, NULL, (void *)SUNXI_USB0_BASE); 538 #endif 539 return 0; 540 } 541 #endif 542 543 #ifdef CONFIG_OF_BOARD_SETUP 544 int ft_board_setup(void *blob, bd_t *bd) 545 { 546 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 547 return sunxi_simplefb_setup(blob); 548 #endif 549 } 550 #endif /* CONFIG_OF_BOARD_SETUP */ 551