1 /* 2 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net> 3 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net> 4 * 5 * (C) Copyright 2007-2011 6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 7 * Tom Cubie <tangliang@allwinnertech.com> 8 * 9 * Some board init for the Allwinner A10-evb board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 14 #include <common.h> 15 #include <mmc.h> 16 #ifdef CONFIG_AXP152_POWER 17 #include <axp152.h> 18 #endif 19 #ifdef CONFIG_AXP209_POWER 20 #include <axp209.h> 21 #endif 22 #ifdef CONFIG_AXP221_POWER 23 #include <axp221.h> 24 #endif 25 #include <asm/arch/clock.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/display.h> 28 #include <asm/arch/dram.h> 29 #include <asm/arch/gpio.h> 30 #include <asm/arch/mmc.h> 31 #include <asm/arch/usb_phy.h> 32 #include <asm/gpio.h> 33 #include <asm/io.h> 34 #include <nand.h> 35 #include <net.h> 36 37 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) 38 /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ 39 int soft_i2c_gpio_sda; 40 int soft_i2c_gpio_scl; 41 42 static int soft_i2c_board_init(void) 43 { 44 int ret; 45 46 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); 47 if (soft_i2c_gpio_sda < 0) { 48 printf("Error invalid soft i2c sda pin: '%s', err %d\n", 49 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda); 50 return soft_i2c_gpio_sda; 51 } 52 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda"); 53 if (ret) { 54 printf("Error requesting soft i2c sda pin: '%s', err %d\n", 55 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret); 56 return ret; 57 } 58 59 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); 60 if (soft_i2c_gpio_scl < 0) { 61 printf("Error invalid soft i2c scl pin: '%s', err %d\n", 62 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl); 63 return soft_i2c_gpio_scl; 64 } 65 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl"); 66 if (ret) { 67 printf("Error requesting soft i2c scl pin: '%s', err %d\n", 68 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret); 69 return ret; 70 } 71 72 return 0; 73 } 74 #else 75 static int soft_i2c_board_init(void) { return 0; } 76 #endif 77 78 DECLARE_GLOBAL_DATA_PTR; 79 80 /* add board specific code here */ 81 int board_init(void) 82 { 83 int id_pfr1, ret; 84 85 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); 86 87 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); 88 debug("id_pfr1: 0x%08x\n", id_pfr1); 89 /* Generic Timer Extension available? */ 90 if ((id_pfr1 >> 16) & 0xf) { 91 debug("Setting CNTFRQ\n"); 92 /* CNTFRQ == 24 MHz */ 93 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); 94 } 95 96 ret = axp_gpio_init(); 97 if (ret) 98 return ret; 99 100 /* Uses dm gpio code so do this here and not in i2c_init_board() */ 101 return soft_i2c_board_init(); 102 } 103 104 int dram_init(void) 105 { 106 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); 107 108 return 0; 109 } 110 111 #if defined(CONFIG_SPL_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) 112 static void nand_pinmux_setup(void) 113 { 114 unsigned int pin; 115 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) 116 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 117 118 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) 119 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); 120 121 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); 122 } 123 124 static void nand_clock_setup(void) 125 { 126 struct sunxi_ccm_reg *const ccm = 127 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; 128 129 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0)); 130 #ifdef CONFIG_MACH_SUN9I 131 setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); 132 #else 133 setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); 134 #endif 135 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); 136 } 137 138 void board_nand_init(void) 139 { 140 nand_pinmux_setup(); 141 nand_clock_setup(); 142 } 143 #endif 144 145 #ifdef CONFIG_GENERIC_MMC 146 static void mmc_pinmux_setup(int sdc) 147 { 148 unsigned int pin; 149 __maybe_unused int pins; 150 151 switch (sdc) { 152 case 0: 153 /* SDC0: PF0-PF5 */ 154 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { 155 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0); 156 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 157 sunxi_gpio_set_drv(pin, 2); 158 } 159 break; 160 161 case 1: 162 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS); 163 164 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 165 if (pins == SUNXI_GPIO_H) { 166 /* SDC1: PH22-PH-27 */ 167 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { 168 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1); 169 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 170 sunxi_gpio_set_drv(pin, 2); 171 } 172 } else { 173 /* SDC1: PG0-PG5 */ 174 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 175 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1); 176 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 177 sunxi_gpio_set_drv(pin, 2); 178 } 179 } 180 #elif defined(CONFIG_MACH_SUN5I) 181 /* SDC1: PG3-PG8 */ 182 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) { 183 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1); 184 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 185 sunxi_gpio_set_drv(pin, 2); 186 } 187 #elif defined(CONFIG_MACH_SUN6I) 188 /* SDC1: PG0-PG5 */ 189 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 190 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1); 191 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 192 sunxi_gpio_set_drv(pin, 2); 193 } 194 #elif defined(CONFIG_MACH_SUN8I) 195 if (pins == SUNXI_GPIO_D) { 196 /* SDC1: PD2-PD7 */ 197 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) { 198 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1); 199 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 200 sunxi_gpio_set_drv(pin, 2); 201 } 202 } else { 203 /* SDC1: PG0-PG5 */ 204 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { 205 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1); 206 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 207 sunxi_gpio_set_drv(pin, 2); 208 } 209 } 210 #endif 211 break; 212 213 case 2: 214 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS); 215 216 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 217 /* SDC2: PC6-PC11 */ 218 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { 219 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 220 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 221 sunxi_gpio_set_drv(pin, 2); 222 } 223 #elif defined(CONFIG_MACH_SUN5I) 224 if (pins == SUNXI_GPIO_E) { 225 /* SDC2: PE4-PE9 */ 226 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) { 227 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2); 228 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 229 sunxi_gpio_set_drv(pin, 2); 230 } 231 } else { 232 /* SDC2: PC6-PC15 */ 233 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 234 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 235 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 236 sunxi_gpio_set_drv(pin, 2); 237 } 238 } 239 #elif defined(CONFIG_MACH_SUN6I) 240 if (pins == SUNXI_GPIO_A) { 241 /* SDC2: PA9-PA14 */ 242 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 243 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2); 244 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 245 sunxi_gpio_set_drv(pin, 2); 246 } 247 } else { 248 /* SDC2: PC6-PC15, PC24 */ 249 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 250 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 251 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 252 sunxi_gpio_set_drv(pin, 2); 253 } 254 255 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2); 256 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 257 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 258 } 259 #elif defined(CONFIG_MACH_SUN8I) 260 /* SDC2: PC5-PC6, PC8-PC16 */ 261 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) { 262 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 263 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 264 sunxi_gpio_set_drv(pin, 2); 265 } 266 267 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) { 268 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2); 269 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 270 sunxi_gpio_set_drv(pin, 2); 271 } 272 #endif 273 break; 274 275 case 3: 276 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS); 277 278 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 279 /* SDC3: PI4-PI9 */ 280 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { 281 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3); 282 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 283 sunxi_gpio_set_drv(pin, 2); 284 } 285 #elif defined(CONFIG_MACH_SUN6I) 286 if (pins == SUNXI_GPIO_A) { 287 /* SDC3: PA9-PA14 */ 288 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) { 289 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3); 290 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 291 sunxi_gpio_set_drv(pin, 2); 292 } 293 } else { 294 /* SDC3: PC6-PC15, PC24 */ 295 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) { 296 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3); 297 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); 298 sunxi_gpio_set_drv(pin, 2); 299 } 300 301 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3); 302 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP); 303 sunxi_gpio_set_drv(SUNXI_GPC(24), 2); 304 } 305 #endif 306 break; 307 308 default: 309 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc); 310 break; 311 } 312 } 313 314 int board_mmc_init(bd_t *bis) 315 { 316 __maybe_unused struct mmc *mmc0, *mmc1; 317 __maybe_unused char buf[512]; 318 319 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT); 320 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); 321 if (!mmc0) 322 return -1; 323 324 #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 325 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA); 326 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); 327 if (!mmc1) 328 return -1; 329 #endif 330 331 #if !defined(CONFIG_SPL_BUILD) && CONFIG_MMC_SUNXI_SLOT_EXTRA == 2 332 /* 333 * On systems with an emmc (mmc2), figure out if we are booting from 334 * the emmc and if we are make it "mmc dev 0" so that boot.scr, etc. 335 * are searched there first. Note we only do this for u-boot proper, 336 * not for the SPL, see spl_boot_device(). 337 */ 338 if (!sunxi_mmc_has_egon_boot_signature(mmc0) && 339 sunxi_mmc_has_egon_boot_signature(mmc1)) { 340 /* Booting from emmc / mmc2, swap */ 341 mmc0->block_dev.dev = 1; 342 mmc1->block_dev.dev = 0; 343 } 344 #endif 345 346 return 0; 347 } 348 #endif 349 350 void i2c_init_board(void) 351 { 352 #ifdef CONFIG_I2C0_ENABLE 353 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) 354 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0); 355 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0); 356 clock_twi_onoff(0, 1); 357 #elif defined(CONFIG_MACH_SUN6I) 358 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0); 359 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0); 360 clock_twi_onoff(0, 1); 361 #elif defined(CONFIG_MACH_SUN8I) 362 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0); 363 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0); 364 clock_twi_onoff(0, 1); 365 #endif 366 #endif 367 368 #ifdef CONFIG_I2C1_ENABLE 369 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 370 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1); 371 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1); 372 clock_twi_onoff(1, 1); 373 #elif defined(CONFIG_MACH_SUN5I) 374 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1); 375 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1); 376 clock_twi_onoff(1, 1); 377 #elif defined(CONFIG_MACH_SUN6I) 378 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1); 379 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1); 380 clock_twi_onoff(1, 1); 381 #elif defined(CONFIG_MACH_SUN8I) 382 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1); 383 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1); 384 clock_twi_onoff(1, 1); 385 #endif 386 #endif 387 388 #ifdef CONFIG_I2C2_ENABLE 389 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) 390 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2); 391 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2); 392 clock_twi_onoff(2, 1); 393 #elif defined(CONFIG_MACH_SUN5I) 394 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2); 395 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2); 396 clock_twi_onoff(2, 1); 397 #elif defined(CONFIG_MACH_SUN6I) 398 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2); 399 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2); 400 clock_twi_onoff(2, 1); 401 #elif defined(CONFIG_MACH_SUN8I) 402 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2); 403 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2); 404 clock_twi_onoff(2, 1); 405 #endif 406 #endif 407 408 #ifdef CONFIG_I2C3_ENABLE 409 #if defined(CONFIG_MACH_SUN6I) 410 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3); 411 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3); 412 clock_twi_onoff(3, 1); 413 #elif defined(CONFIG_MACH_SUN7I) 414 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3); 415 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3); 416 clock_twi_onoff(3, 1); 417 #endif 418 #endif 419 420 #ifdef CONFIG_I2C4_ENABLE 421 #if defined(CONFIG_MACH_SUN7I) 422 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4); 423 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4); 424 clock_twi_onoff(4, 1); 425 #endif 426 #endif 427 } 428 429 #ifdef CONFIG_SPL_BUILD 430 void sunxi_board_init(void) 431 { 432 int power_failed = 0; 433 unsigned long ramsize; 434 435 #ifdef CONFIG_AXP152_POWER 436 power_failed = axp152_init(); 437 power_failed |= axp152_set_dcdc2(1400); 438 power_failed |= axp152_set_dcdc3(1500); 439 power_failed |= axp152_set_dcdc4(1250); 440 power_failed |= axp152_set_ldo2(3000); 441 #endif 442 #ifdef CONFIG_AXP209_POWER 443 power_failed |= axp209_init(); 444 power_failed |= axp209_set_dcdc2(1400); 445 power_failed |= axp209_set_dcdc3(1250); 446 power_failed |= axp209_set_ldo2(3000); 447 power_failed |= axp209_set_ldo3(2800); 448 power_failed |= axp209_set_ldo4(2800); 449 #endif 450 #ifdef CONFIG_AXP221_POWER 451 power_failed = axp221_init(); 452 power_failed |= axp221_set_dcdc1(CONFIG_AXP221_DCDC1_VOLT); 453 power_failed |= axp221_set_dcdc2(CONFIG_AXP221_DCDC2_VOLT); 454 power_failed |= axp221_set_dcdc3(1200); /* VDD-CPU */ 455 #ifdef CONFIG_MACH_SUN6I 456 power_failed |= axp221_set_dcdc4(1200); /* A31:VDD-SYS */ 457 #else 458 power_failed |= axp221_set_dcdc4(0); /* A23:unused */ 459 #endif 460 power_failed |= axp221_set_dcdc5(1500); /* VCC-DRAM */ 461 power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT); 462 power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT); 463 power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT); 464 power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT); 465 power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT); 466 power_failed |= axp221_set_eldo(3, CONFIG_AXP221_ELDO3_VOLT); 467 #endif 468 469 printf("DRAM:"); 470 ramsize = sunxi_dram_init(); 471 printf(" %lu MiB\n", ramsize >> 20); 472 if (!ramsize) 473 hang(); 474 475 /* 476 * Only clock up the CPU to full speed if we are reasonably 477 * assured it's being powered with suitable core voltage 478 */ 479 if (!power_failed) 480 clock_set_pll1(CONFIG_SYS_CLK_FREQ); 481 else 482 printf("Failed to set core voltage! Can't set CPU frequency\n"); 483 } 484 #endif 485 486 #ifdef CONFIG_USB_GADGET 487 int g_dnl_board_usb_cable_connected(void) 488 { 489 return sunxi_usb_phy_vbus_detect(0); 490 } 491 #endif 492 493 #ifdef CONFIG_SERIAL_TAG 494 void get_board_serial(struct tag_serialnr *serialnr) 495 { 496 char *serial_string; 497 unsigned long long serial; 498 499 serial_string = getenv("serial#"); 500 501 if (serial_string) { 502 serial = simple_strtoull(serial_string, NULL, 16); 503 504 serialnr->high = (unsigned int) (serial >> 32); 505 serialnr->low = (unsigned int) (serial & 0xffffffff); 506 } else { 507 serialnr->high = 0; 508 serialnr->low = 0; 509 } 510 } 511 #endif 512 513 #ifdef CONFIG_MISC_INIT_R 514 int misc_init_r(void) 515 { 516 char serial_string[17] = { 0 }; 517 unsigned int sid[4]; 518 uint8_t mac_addr[6]; 519 int ret; 520 521 ret = sunxi_get_sid(sid); 522 if (ret == 0 && sid[0] != 0 && sid[3] != 0) { 523 if (!getenv("ethaddr")) { 524 /* Non OUI / registered MAC address */ 525 mac_addr[0] = 0x02; 526 mac_addr[1] = (sid[0] >> 0) & 0xff; 527 mac_addr[2] = (sid[3] >> 24) & 0xff; 528 mac_addr[3] = (sid[3] >> 16) & 0xff; 529 mac_addr[4] = (sid[3] >> 8) & 0xff; 530 mac_addr[5] = (sid[3] >> 0) & 0xff; 531 532 eth_setenv_enetaddr("ethaddr", mac_addr); 533 } 534 535 if (!getenv("serial#")) { 536 snprintf(serial_string, sizeof(serial_string), 537 "%08x%08x", sid[0], sid[3]); 538 539 setenv("serial#", serial_string); 540 } 541 } 542 543 #ifndef CONFIG_MACH_SUN9I 544 ret = sunxi_usb_phy_probe(); 545 if (ret) 546 return ret; 547 #endif 548 sunxi_musb_board_init(); 549 550 return 0; 551 } 552 #endif 553 554 #ifdef CONFIG_OF_BOARD_SETUP 555 int ft_board_setup(void *blob, bd_t *bd) 556 { 557 #ifdef CONFIG_VIDEO_DT_SIMPLEFB 558 return sunxi_simplefb_setup(blob); 559 #endif 560 } 561 #endif /* CONFIG_OF_BOARD_SETUP */ 562