1ae9996c8SStefan Roese /* 2ae9996c8SStefan Roese * Altera SoCFPGA SDRAM configuration 3ae9996c8SStefan Roese * 4ae9996c8SStefan Roese * SPDX-License-Identifier: BSD-3-Clause 5ae9996c8SStefan Roese */ 6ae9996c8SStefan Roese 7ae9996c8SStefan Roese #ifndef __SOCFPGA_SDRAM_CONFIG_H__ 8ae9996c8SStefan Roese #define __SOCFPGA_SDRAM_CONFIG_H__ 9ae9996c8SStefan Roese 10ae9996c8SStefan Roese /* SDRAM configuration */ 11ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A 12ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 13ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 14ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 15ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 16ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 17ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 18ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 19ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 20ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 21ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 22ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 23ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 24ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 25ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 26ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 27ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 28ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 29ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 30ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 31ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 32ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 33ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 34ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 35ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 36ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 37ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 38ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 39ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 40ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 41ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 42ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 43ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 44ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 45ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 46ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 47ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 48ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 49ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 50ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 51ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 52*20293639SChin Liang See #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 53*20293639SChin Liang See #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 54*20293639SChin Liang See #define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 55ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 56ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 57ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 58ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 59ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 60ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 61ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 62ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 63ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 64ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 65ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 66ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 67ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 68ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 69ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 70ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 71ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 72ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 73ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 74ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 75ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 76ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 77ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 78ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 79ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 80ae9996c8SStefan Roese #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 81ae9996c8SStefan Roese 82ae9996c8SStefan Roese /* Sequencer auto configuration */ 83ae9996c8SStefan Roese #define RW_MGR_ACTIVATE_0_AND_1 0x0D 84ae9996c8SStefan Roese #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E 85ae9996c8SStefan Roese #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 86ae9996c8SStefan Roese #define RW_MGR_ACTIVATE_1 0x0F 87ae9996c8SStefan Roese #define RW_MGR_CLEAR_DQS_ENABLE 0x49 88ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_READ 0x4C 89ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_READ_CONT 0x54 90ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_WRITE 0x18 91ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B 92ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F 93ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 94ae9996c8SStefan Roese #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D 95ae9996c8SStefan Roese #define RW_MGR_IDLE 0x00 96ae9996c8SStefan Roese #define RW_MGR_IDLE_LOOP1 0x7B 97ae9996c8SStefan Roese #define RW_MGR_IDLE_LOOP2 0x7A 98ae9996c8SStefan Roese #define RW_MGR_INIT_RESET_0_CKE_0 0x6F 99ae9996c8SStefan Roese #define RW_MGR_INIT_RESET_1_CKE_0 0x74 100ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0 0x22 101ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 102ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 103ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 104ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 105ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 106ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 107ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 108ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 109ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 110ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 111ae9996c8SStefan Roese #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 112ae9996c8SStefan Roese #define RW_MGR_MRS0_DLL_RESET 0x02 113ae9996c8SStefan Roese #define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 114ae9996c8SStefan Roese #define RW_MGR_MRS0_USER 0x07 115ae9996c8SStefan Roese #define RW_MGR_MRS0_USER_MIRR 0x0C 116ae9996c8SStefan Roese #define RW_MGR_MRS1 0x03 117ae9996c8SStefan Roese #define RW_MGR_MRS1_MIRR 0x09 118ae9996c8SStefan Roese #define RW_MGR_MRS2 0x04 119ae9996c8SStefan Roese #define RW_MGR_MRS2_MIRR 0x0A 120ae9996c8SStefan Roese #define RW_MGR_MRS3 0x05 121ae9996c8SStefan Roese #define RW_MGR_MRS3_MIRR 0x0B 122ae9996c8SStefan Roese #define RW_MGR_PRECHARGE_ALL 0x12 123ae9996c8SStefan Roese #define RW_MGR_READ_B2B 0x59 124ae9996c8SStefan Roese #define RW_MGR_READ_B2B_WAIT1 0x61 125ae9996c8SStefan Roese #define RW_MGR_READ_B2B_WAIT2 0x6B 126ae9996c8SStefan Roese #define RW_MGR_REFRESH_ALL 0x14 127ae9996c8SStefan Roese #define RW_MGR_RETURN 0x01 128ae9996c8SStefan Roese #define RW_MGR_SGLE_READ 0x7D 129ae9996c8SStefan Roese #define RW_MGR_ZQCL 0x06 130ae9996c8SStefan Roese 131ae9996c8SStefan Roese /* Sequencer defines configuration */ 132ae9996c8SStefan Roese #define AFI_RATE_RATIO 1 133ae9996c8SStefan Roese #define CALIB_LFIFO_OFFSET 7 134ae9996c8SStefan Roese #define CALIB_VFIFO_OFFSET 5 135ae9996c8SStefan Roese #define ENABLE_SUPER_QUICK_CALIBRATION 0 136ae9996c8SStefan Roese #define IO_DELAY_PER_DCHAIN_TAP 25 137ae9996c8SStefan Roese #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 138ae9996c8SStefan Roese #define IO_DELAY_PER_OPA_TAP 312 139ae9996c8SStefan Roese #define IO_DLL_CHAIN_LENGTH 8 140ae9996c8SStefan Roese #define IO_DQDQS_OUT_PHASE_MAX 0 141ae9996c8SStefan Roese #define IO_DQS_EN_DELAY_MAX 31 142ae9996c8SStefan Roese #define IO_DQS_EN_DELAY_OFFSET 0 143ae9996c8SStefan Roese #define IO_DQS_EN_PHASE_MAX 7 144ae9996c8SStefan Roese #define IO_DQS_IN_DELAY_MAX 31 145ae9996c8SStefan Roese #define IO_DQS_IN_RESERVE 4 146ae9996c8SStefan Roese #define IO_DQS_OUT_RESERVE 4 147ae9996c8SStefan Roese #define IO_IO_IN_DELAY_MAX 31 148ae9996c8SStefan Roese #define IO_IO_OUT1_DELAY_MAX 31 149ae9996c8SStefan Roese #define IO_IO_OUT2_DELAY_MAX 0 150ae9996c8SStefan Roese #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 151ae9996c8SStefan Roese #define MAX_LATENCY_COUNT_WIDTH 5 152ae9996c8SStefan Roese #define READ_VALID_FIFO_SIZE 16 153ae9996c8SStefan Roese #define REG_FILE_INIT_SEQ_SIGNATURE 0x55550496 154ae9996c8SStefan Roese #define RW_MGR_MEM_ADDRESS_MIRRORING 0 155ae9996c8SStefan Roese #define RW_MGR_MEM_DATA_MASK_WIDTH 4 156ae9996c8SStefan Roese #define RW_MGR_MEM_DATA_WIDTH 32 157ae9996c8SStefan Roese #define RW_MGR_MEM_DQ_PER_READ_DQS 8 158ae9996c8SStefan Roese #define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 159ae9996c8SStefan Roese #define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 160ae9996c8SStefan Roese #define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 161ae9996c8SStefan Roese #define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 162ae9996c8SStefan Roese #define RW_MGR_MEM_NUMBER_OF_RANKS 1 163ae9996c8SStefan Roese #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 164ae9996c8SStefan Roese #define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 165ae9996c8SStefan Roese #define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 166ae9996c8SStefan Roese #define TINIT_CNTR0_VAL 99 167ae9996c8SStefan Roese #define TINIT_CNTR1_VAL 32 168ae9996c8SStefan Roese #define TINIT_CNTR2_VAL 32 169ae9996c8SStefan Roese #define TRESET_CNTR0_VAL 99 170ae9996c8SStefan Roese #define TRESET_CNTR1_VAL 99 171ae9996c8SStefan Roese #define TRESET_CNTR2_VAL 10 172ae9996c8SStefan Roese 173ae9996c8SStefan Roese /* Sequencer ac_rom_init configuration */ 174ae9996c8SStefan Roese const u32 ac_rom_init[] = { 175ae9996c8SStefan Roese 0x20700000, 176ae9996c8SStefan Roese 0x20780000, 177ae9996c8SStefan Roese 0x10080421, 178ae9996c8SStefan Roese 0x10080520, 179ae9996c8SStefan Roese 0x10090044, 180ae9996c8SStefan Roese 0x100a0008, 181ae9996c8SStefan Roese 0x100b0000, 182ae9996c8SStefan Roese 0x10380400, 183ae9996c8SStefan Roese 0x10080441, 184ae9996c8SStefan Roese 0x100804c0, 185ae9996c8SStefan Roese 0x100a0024, 186ae9996c8SStefan Roese 0x10090010, 187ae9996c8SStefan Roese 0x100b0000, 188ae9996c8SStefan Roese 0x30780000, 189ae9996c8SStefan Roese 0x38780000, 190ae9996c8SStefan Roese 0x30780000, 191ae9996c8SStefan Roese 0x10680000, 192ae9996c8SStefan Roese 0x106b0000, 193ae9996c8SStefan Roese 0x10280400, 194ae9996c8SStefan Roese 0x10480000, 195ae9996c8SStefan Roese 0x1c980000, 196ae9996c8SStefan Roese 0x1c9b0000, 197ae9996c8SStefan Roese 0x1c980008, 198ae9996c8SStefan Roese 0x1c9b0008, 199ae9996c8SStefan Roese 0x38f80000, 200ae9996c8SStefan Roese 0x3cf80000, 201ae9996c8SStefan Roese 0x38780000, 202ae9996c8SStefan Roese 0x18180000, 203ae9996c8SStefan Roese 0x18980000, 204ae9996c8SStefan Roese 0x13580000, 205ae9996c8SStefan Roese 0x135b0000, 206ae9996c8SStefan Roese 0x13580008, 207ae9996c8SStefan Roese 0x135b0008, 208ae9996c8SStefan Roese 0x33780000, 209ae9996c8SStefan Roese 0x10580008, 210ae9996c8SStefan Roese 0x10780000 211ae9996c8SStefan Roese }; 212ae9996c8SStefan Roese 213ae9996c8SStefan Roese /* Sequencer inst_rom_init configuration */ 214ae9996c8SStefan Roese const u32 inst_rom_init[] = { 215ae9996c8SStefan Roese 0x80000, 216ae9996c8SStefan Roese 0x80680, 217ae9996c8SStefan Roese 0x8180, 218ae9996c8SStefan Roese 0x8200, 219ae9996c8SStefan Roese 0x8280, 220ae9996c8SStefan Roese 0x8300, 221ae9996c8SStefan Roese 0x8380, 222ae9996c8SStefan Roese 0x8100, 223ae9996c8SStefan Roese 0x8480, 224ae9996c8SStefan Roese 0x8500, 225ae9996c8SStefan Roese 0x8580, 226ae9996c8SStefan Roese 0x8600, 227ae9996c8SStefan Roese 0x8400, 228ae9996c8SStefan Roese 0x800, 229ae9996c8SStefan Roese 0x8680, 230ae9996c8SStefan Roese 0x880, 231ae9996c8SStefan Roese 0xa680, 232ae9996c8SStefan Roese 0x80680, 233ae9996c8SStefan Roese 0x900, 234ae9996c8SStefan Roese 0x80680, 235ae9996c8SStefan Roese 0x980, 236ae9996c8SStefan Roese 0xa680, 237ae9996c8SStefan Roese 0x8680, 238ae9996c8SStefan Roese 0x80680, 239ae9996c8SStefan Roese 0xb68, 240ae9996c8SStefan Roese 0xcce8, 241ae9996c8SStefan Roese 0xae8, 242ae9996c8SStefan Roese 0x8ce8, 243ae9996c8SStefan Roese 0xb88, 244ae9996c8SStefan Roese 0xec88, 245ae9996c8SStefan Roese 0xa08, 246ae9996c8SStefan Roese 0xac88, 247ae9996c8SStefan Roese 0x80680, 248ae9996c8SStefan Roese 0xce00, 249ae9996c8SStefan Roese 0xcd80, 250ae9996c8SStefan Roese 0xe700, 251ae9996c8SStefan Roese 0xc00, 252ae9996c8SStefan Roese 0x20ce0, 253ae9996c8SStefan Roese 0x20ce0, 254ae9996c8SStefan Roese 0x20ce0, 255ae9996c8SStefan Roese 0x20ce0, 256ae9996c8SStefan Roese 0xd00, 257ae9996c8SStefan Roese 0x680, 258ae9996c8SStefan Roese 0x680, 259ae9996c8SStefan Roese 0x680, 260ae9996c8SStefan Roese 0x680, 261ae9996c8SStefan Roese 0x60e80, 262ae9996c8SStefan Roese 0x61080, 263ae9996c8SStefan Roese 0x61080, 264ae9996c8SStefan Roese 0x61080, 265ae9996c8SStefan Roese 0xa680, 266ae9996c8SStefan Roese 0x8680, 267ae9996c8SStefan Roese 0x80680, 268ae9996c8SStefan Roese 0xce00, 269ae9996c8SStefan Roese 0xcd80, 270ae9996c8SStefan Roese 0xe700, 271ae9996c8SStefan Roese 0xc00, 272ae9996c8SStefan Roese 0x30ce0, 273ae9996c8SStefan Roese 0x30ce0, 274ae9996c8SStefan Roese 0x30ce0, 275ae9996c8SStefan Roese 0x30ce0, 276ae9996c8SStefan Roese 0xd00, 277ae9996c8SStefan Roese 0x680, 278ae9996c8SStefan Roese 0x680, 279ae9996c8SStefan Roese 0x680, 280ae9996c8SStefan Roese 0x680, 281ae9996c8SStefan Roese 0x70e80, 282ae9996c8SStefan Roese 0x71080, 283ae9996c8SStefan Roese 0x71080, 284ae9996c8SStefan Roese 0x71080, 285ae9996c8SStefan Roese 0xa680, 286ae9996c8SStefan Roese 0x8680, 287ae9996c8SStefan Roese 0x80680, 288ae9996c8SStefan Roese 0x1158, 289ae9996c8SStefan Roese 0x6d8, 290ae9996c8SStefan Roese 0x80680, 291ae9996c8SStefan Roese 0x1168, 292ae9996c8SStefan Roese 0x7e8, 293ae9996c8SStefan Roese 0x7e8, 294ae9996c8SStefan Roese 0x87e8, 295ae9996c8SStefan Roese 0x40fe8, 296ae9996c8SStefan Roese 0x410e8, 297ae9996c8SStefan Roese 0x410e8, 298ae9996c8SStefan Roese 0x410e8, 299ae9996c8SStefan Roese 0x1168, 300ae9996c8SStefan Roese 0x7e8, 301ae9996c8SStefan Roese 0x7e8, 302ae9996c8SStefan Roese 0xa7e8, 303ae9996c8SStefan Roese 0x80680, 304ae9996c8SStefan Roese 0x40e88, 305ae9996c8SStefan Roese 0x41088, 306ae9996c8SStefan Roese 0x41088, 307ae9996c8SStefan Roese 0x41088, 308ae9996c8SStefan Roese 0x40f68, 309ae9996c8SStefan Roese 0x410e8, 310ae9996c8SStefan Roese 0x410e8, 311ae9996c8SStefan Roese 0x410e8, 312ae9996c8SStefan Roese 0xa680, 313ae9996c8SStefan Roese 0x40fe8, 314ae9996c8SStefan Roese 0x410e8, 315ae9996c8SStefan Roese 0x410e8, 316ae9996c8SStefan Roese 0x410e8, 317ae9996c8SStefan Roese 0x41008, 318ae9996c8SStefan Roese 0x41088, 319ae9996c8SStefan Roese 0x41088, 320ae9996c8SStefan Roese 0x41088, 321ae9996c8SStefan Roese 0x1100, 322ae9996c8SStefan Roese 0xc680, 323ae9996c8SStefan Roese 0x8680, 324ae9996c8SStefan Roese 0xe680, 325ae9996c8SStefan Roese 0x80680, 326ae9996c8SStefan Roese 0x0, 327ae9996c8SStefan Roese 0x8000, 328ae9996c8SStefan Roese 0xa000, 329ae9996c8SStefan Roese 0xc000, 330ae9996c8SStefan Roese 0x80000, 331ae9996c8SStefan Roese 0x80, 332ae9996c8SStefan Roese 0x8080, 333ae9996c8SStefan Roese 0xa080, 334ae9996c8SStefan Roese 0xc080, 335ae9996c8SStefan Roese 0x80080, 336ae9996c8SStefan Roese 0x9180, 337ae9996c8SStefan Roese 0x8680, 338ae9996c8SStefan Roese 0xa680, 339ae9996c8SStefan Roese 0x80680, 340ae9996c8SStefan Roese 0x40f08, 341ae9996c8SStefan Roese 0x80680 342ae9996c8SStefan Roese }; 343ae9996c8SStefan Roese 344ae9996c8SStefan Roese #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ 345