1*ae9996c8SStefan Roese /* 2*ae9996c8SStefan Roese * Altera SoCFPGA Clock and PLL configuration 3*ae9996c8SStefan Roese * 4*ae9996c8SStefan Roese * SPDX-License-Identifier: BSD-3-Clause 5*ae9996c8SStefan Roese */ 6*ae9996c8SStefan Roese 7*ae9996c8SStefan Roese #ifndef __SOCFPGA_PLL_CONFIG_H__ 8*ae9996c8SStefan Roese #define __SOCFPGA_PLL_CONFIG_H__ 9*ae9996c8SStefan Roese 10*ae9996c8SStefan Roese #define CONFIG_HPS_DBCTRL_STAYOSC1 1 11*ae9996c8SStefan Roese 12*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 13*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 14*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 15*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 16*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 17*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 18*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 19*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 20*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 21*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 22*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 23*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 24*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 25*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 26*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 27*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 28*ae9996c8SStefan Roese #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 29*ae9996c8SStefan Roese 30*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 31*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 32*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 33*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 34*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 35*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 36*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 37*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 38*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 39*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 40*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 41*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 42*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 43*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 44*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 45*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 46*ae9996c8SStefan Roese #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 47*ae9996c8SStefan Roese 48*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 49*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 50*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 51*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 52*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 53*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 54*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 55*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 56*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 57*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 58*ae9996c8SStefan Roese #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 59*ae9996c8SStefan Roese 60*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_OSC1_HZ 25000000 61*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_OSC2_HZ 25000000 62*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 63*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 64*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 65*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 66*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 67*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_EMAC0_HZ 1953125 68*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 69*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 70*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_NAND_HZ 50000000 71*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 72*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_QSPI_HZ 400000000 73*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_SPIM_HZ 12500000 74*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_CAN0_HZ 12500000 75*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_CAN1_HZ 12500000 76*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_GPIODB_HZ 32000 77*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 78*ae9996c8SStefan Roese #define CONFIG_HPS_CLK_L4_SP_HZ 100000000 79*ae9996c8SStefan Roese 80*ae9996c8SStefan Roese #define CONFIG_HPS_ALTERAGRP_MPUCLK 1 81*ae9996c8SStefan Roese #define CONFIG_HPS_ALTERAGRP_MAINCLK 3 82*ae9996c8SStefan Roese #define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 83*ae9996c8SStefan Roese 84*ae9996c8SStefan Roese 85*ae9996c8SStefan Roese #endif /* __SOCFPGA_PLL_CONFIG_H__ */ 86