1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com> 7 * 8 * Based on SPL code from Solidrun tree, which is: 9 * Author: Tungyi Lin <tungyilin1127@gmail.com> 10 * 11 * Derived from EDM_CF_IMX6 code by TechNexion,Inc 12 * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <asm/arch/clock.h> 18 #include <asm/arch/imx-regs.h> 19 #include <asm/arch/iomux.h> 20 #include <asm/arch/mx6-pins.h> 21 #include <asm/arch/mxc_hdmi.h> 22 #include <asm/errno.h> 23 #include <asm/gpio.h> 24 #include <asm/imx-common/iomux-v3.h> 25 #include <asm/imx-common/video.h> 26 #include <mmc.h> 27 #include <fsl_esdhc.h> 28 #include <miiphy.h> 29 #include <netdev.h> 30 #include <asm/arch/crm_regs.h> 31 #include <asm/io.h> 32 #include <asm/arch/sys_proto.h> 33 #include <spl.h> 34 #include <usb.h> 35 #include <usb/ehci-fsl.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 40 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 44 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 45 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 46 47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 49 50 #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ 51 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 52 53 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ 54 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 55 56 #define ETH_PHY_RESET IMX_GPIO_NR(4, 15) 57 #define USB_H1_VBUS IMX_GPIO_NR(1, 0) 58 59 int dram_init(void) 60 { 61 gd->ram_size = imx_ddr_size(); 62 return 0; 63 } 64 65 static iomux_v3_cfg_t const uart1_pads[] = { 66 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 67 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 68 }; 69 70 static iomux_v3_cfg_t const usdhc2_pads[] = { 71 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 72 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 73 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 74 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 75 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 76 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 77 }; 78 79 static iomux_v3_cfg_t const hb_cbi_sense[] = { 80 /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ 81 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), 82 IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL)), 83 }; 84 85 static iomux_v3_cfg_t const usb_pads[] = { 86 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), 87 }; 88 89 static void setup_iomux_uart(void) 90 { 91 SETUP_IOMUX_PADS(uart1_pads); 92 } 93 94 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 95 {USDHC2_BASE_ADDR}, 96 }; 97 98 int board_mmc_getcd(struct mmc *mmc) 99 { 100 return 1; /* uSDHC2 is always present */ 101 } 102 103 int board_mmc_init(bd_t *bis) 104 { 105 SETUP_IOMUX_PADS(usdhc2_pads); 106 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 107 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 108 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 109 110 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 111 } 112 113 static iomux_v3_cfg_t const enet_pads[] = { 114 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 115 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 116 /* AR8035 reset */ 117 IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 118 /* AR8035 interrupt */ 119 IOMUX_PADS(PAD_DI0_PIN2__GPIO4_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), 120 /* GPIO16 -> AR8035 25MHz */ 121 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), 122 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL)), 123 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 124 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 125 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 126 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 127 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 128 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 129 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK)), 130 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 131 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 132 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 133 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 134 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 135 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD)), 136 }; 137 138 static void setup_iomux_enet(void) 139 { 140 SETUP_IOMUX_PADS(enet_pads); 141 142 gpio_direction_output(ETH_PHY_RESET, 0); 143 mdelay(2); 144 gpio_set_value(ETH_PHY_RESET, 1); 145 } 146 147 int board_phy_config(struct phy_device *phydev) 148 { 149 if (phydev->drv->config) 150 phydev->drv->config(phydev); 151 152 return 0; 153 } 154 155 int board_eth_init(bd_t *bis) 156 { 157 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 158 159 int ret = enable_fec_anatop_clock(ENET_25MHZ); 160 if (ret) 161 return ret; 162 163 /* set gpr1[ENET_CLK_SEL] */ 164 setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 165 166 setup_iomux_enet(); 167 168 return cpu_eth_init(bis); 169 } 170 171 #ifdef CONFIG_VIDEO_IPUV3 172 static void do_enable_hdmi(struct display_info_t const *dev) 173 { 174 imx_enable_hdmi_phy(); 175 } 176 177 struct display_info_t const displays[] = { 178 { 179 .bus = -1, 180 .addr = 0, 181 .pixfmt = IPU_PIX_FMT_RGB24, 182 .detect = detect_hdmi, 183 .enable = do_enable_hdmi, 184 .mode = { 185 .name = "HDMI", 186 /* 1024x768@60Hz (VESA)*/ 187 .refresh = 60, 188 .xres = 1024, 189 .yres = 768, 190 .pixclock = 15384, 191 .left_margin = 160, 192 .right_margin = 24, 193 .upper_margin = 29, 194 .lower_margin = 3, 195 .hsync_len = 136, 196 .vsync_len = 6, 197 .sync = FB_SYNC_EXT, 198 .vmode = FB_VMODE_NONINTERLACED 199 } 200 } 201 }; 202 203 size_t display_count = ARRAY_SIZE(displays); 204 205 static int setup_display(void) 206 { 207 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 208 int reg; 209 int timeout = 100000; 210 211 enable_ipu_clock(); 212 imx_setup_hdmi(); 213 214 /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */ 215 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN); 216 217 reg = readl(&ccm->analog_pll_video); 218 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; 219 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37); 220 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; 221 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1); 222 writel(reg, &ccm->analog_pll_video); 223 224 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num); 225 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom); 226 227 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; 228 writel(reg, &ccm->analog_pll_video); 229 230 while (timeout--) 231 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 232 break; 233 if (timeout < 0) { 234 printf("Warning: video pll lock timeout!\n"); 235 return -ETIMEDOUT; 236 } 237 238 reg = readl(&ccm->analog_pll_video); 239 reg |= BM_ANADIG_PLL_VIDEO_ENABLE; 240 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; 241 writel(reg, &ccm->analog_pll_video); 242 243 /* gate ipu1_di0_clk */ 244 clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 245 246 /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */ 247 reg = readl(&ccm->chsccdr); 248 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | 249 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK | 250 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); 251 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) | 252 (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) | 253 (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 254 writel(reg, &ccm->chsccdr); 255 256 /* enable ipu1_di0_clk */ 257 setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK); 258 259 return 0; 260 } 261 #endif /* CONFIG_VIDEO_IPUV3 */ 262 263 #ifdef CONFIG_USB_EHCI_MX6 264 static void setup_usb(void) 265 { 266 SETUP_IOMUX_PADS(usb_pads); 267 } 268 269 int board_ehci_hcd_init(int port) 270 { 271 if (port == 1) 272 gpio_direction_output(USB_H1_VBUS, 1); 273 274 return 0; 275 } 276 #endif 277 278 int board_early_init_f(void) 279 { 280 int ret = 0; 281 setup_iomux_uart(); 282 283 #ifdef CONFIG_VIDEO_IPUV3 284 ret = setup_display(); 285 #endif 286 287 #ifdef CONFIG_USB_EHCI_MX6 288 setup_usb(); 289 #endif 290 return ret; 291 } 292 293 int board_init(void) 294 { 295 /* address of boot parameters */ 296 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 297 298 return 0; 299 } 300 301 static bool is_hummingboard(void) 302 { 303 int val1, val2; 304 305 SETUP_IOMUX_PADS(hb_cbi_sense); 306 307 gpio_direction_input(IMX_GPIO_NR(4, 9)); 308 gpio_direction_input(IMX_GPIO_NR(3, 4)); 309 310 val1 = gpio_get_value(IMX_GPIO_NR(4, 9)); 311 val2 = gpio_get_value(IMX_GPIO_NR(3, 4)); 312 313 /* 314 * Machine selection - 315 * Machine val1, val2 316 * ------------------------- 317 * HB rev 3.x x 0 318 * CBi 0 1 319 * HB 1 1 320 */ 321 322 if (val2 == 0) 323 return true; 324 else if (val1 == 0) 325 return false; 326 else 327 return true; 328 } 329 330 int checkboard(void) 331 { 332 if (is_hummingboard()) 333 puts("Board: MX6 Hummingboard\n"); 334 else 335 puts("Board: MX6 Cubox-i\n"); 336 337 return 0; 338 } 339 340 static bool is_mx6q(void) 341 { 342 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) 343 return true; 344 else 345 return false; 346 } 347 348 int board_late_init(void) 349 { 350 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 351 if (is_hummingboard()) 352 setenv("board_name", "HUMMINGBOARD"); 353 else 354 setenv("board_name", "CUBOXI"); 355 356 if (is_mx6q()) 357 setenv("board_rev", "MX6Q"); 358 else 359 setenv("board_rev", "MX6DL"); 360 #endif 361 362 return 0; 363 } 364 365 #ifdef CONFIG_SPL_BUILD 366 #include <asm/arch/mx6-ddr.h> 367 static const struct mx6dq_iomux_ddr_regs mx6q_ddr_ioregs = { 368 .dram_sdclk_0 = 0x00020030, 369 .dram_sdclk_1 = 0x00020030, 370 .dram_cas = 0x00020030, 371 .dram_ras = 0x00020030, 372 .dram_reset = 0x00020030, 373 .dram_sdcke0 = 0x00003000, 374 .dram_sdcke1 = 0x00003000, 375 .dram_sdba2 = 0x00000000, 376 .dram_sdodt0 = 0x00003030, 377 .dram_sdodt1 = 0x00003030, 378 .dram_sdqs0 = 0x00000030, 379 .dram_sdqs1 = 0x00000030, 380 .dram_sdqs2 = 0x00000030, 381 .dram_sdqs3 = 0x00000030, 382 .dram_sdqs4 = 0x00000030, 383 .dram_sdqs5 = 0x00000030, 384 .dram_sdqs6 = 0x00000030, 385 .dram_sdqs7 = 0x00000030, 386 .dram_dqm0 = 0x00020030, 387 .dram_dqm1 = 0x00020030, 388 .dram_dqm2 = 0x00020030, 389 .dram_dqm3 = 0x00020030, 390 .dram_dqm4 = 0x00020030, 391 .dram_dqm5 = 0x00020030, 392 .dram_dqm6 = 0x00020030, 393 .dram_dqm7 = 0x00020030, 394 }; 395 396 static const struct mx6sdl_iomux_ddr_regs mx6dl_ddr_ioregs = { 397 .dram_sdclk_0 = 0x00000028, 398 .dram_sdclk_1 = 0x00000028, 399 .dram_cas = 0x00000028, 400 .dram_ras = 0x00000028, 401 .dram_reset = 0x000c0028, 402 .dram_sdcke0 = 0x00003000, 403 .dram_sdcke1 = 0x00003000, 404 .dram_sdba2 = 0x00000000, 405 .dram_sdodt0 = 0x00003030, 406 .dram_sdodt1 = 0x00003030, 407 .dram_sdqs0 = 0x00000028, 408 .dram_sdqs1 = 0x00000028, 409 .dram_sdqs2 = 0x00000028, 410 .dram_sdqs3 = 0x00000028, 411 .dram_sdqs4 = 0x00000028, 412 .dram_sdqs5 = 0x00000028, 413 .dram_sdqs6 = 0x00000028, 414 .dram_sdqs7 = 0x00000028, 415 .dram_dqm0 = 0x00000028, 416 .dram_dqm1 = 0x00000028, 417 .dram_dqm2 = 0x00000028, 418 .dram_dqm3 = 0x00000028, 419 .dram_dqm4 = 0x00000028, 420 .dram_dqm5 = 0x00000028, 421 .dram_dqm6 = 0x00000028, 422 .dram_dqm7 = 0x00000028, 423 }; 424 425 static const struct mx6dq_iomux_grp_regs mx6q_grp_ioregs = { 426 .grp_ddr_type = 0x000C0000, 427 .grp_ddrmode_ctl = 0x00020000, 428 .grp_ddrpke = 0x00000000, 429 .grp_addds = 0x00000030, 430 .grp_ctlds = 0x00000030, 431 .grp_ddrmode = 0x00020000, 432 .grp_b0ds = 0x00000030, 433 .grp_b1ds = 0x00000030, 434 .grp_b2ds = 0x00000030, 435 .grp_b3ds = 0x00000030, 436 .grp_b4ds = 0x00000030, 437 .grp_b5ds = 0x00000030, 438 .grp_b6ds = 0x00000030, 439 .grp_b7ds = 0x00000030, 440 }; 441 442 static const struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 443 .grp_ddr_type = 0x000c0000, 444 .grp_ddrmode_ctl = 0x00020000, 445 .grp_ddrpke = 0x00000000, 446 .grp_addds = 0x00000028, 447 .grp_ctlds = 0x00000028, 448 .grp_ddrmode = 0x00020000, 449 .grp_b0ds = 0x00000028, 450 .grp_b1ds = 0x00000028, 451 .grp_b2ds = 0x00000028, 452 .grp_b3ds = 0x00000028, 453 .grp_b4ds = 0x00000028, 454 .grp_b5ds = 0x00000028, 455 .grp_b6ds = 0x00000028, 456 .grp_b7ds = 0x00000028, 457 }; 458 459 /* microSOM with Dual processor and 1GB memory */ 460 static const struct mx6_mmdc_calibration mx6q_1g_mmcd_calib = { 461 .p0_mpwldectrl0 = 0x00000000, 462 .p0_mpwldectrl1 = 0x00000000, 463 .p1_mpwldectrl0 = 0x00000000, 464 .p1_mpwldectrl1 = 0x00000000, 465 .p0_mpdgctrl0 = 0x0314031c, 466 .p0_mpdgctrl1 = 0x023e0304, 467 .p1_mpdgctrl0 = 0x03240330, 468 .p1_mpdgctrl1 = 0x03180260, 469 .p0_mprddlctl = 0x3630323c, 470 .p1_mprddlctl = 0x3436283a, 471 .p0_mpwrdlctl = 0x36344038, 472 .p1_mpwrdlctl = 0x422a423c, 473 }; 474 475 /* microSOM with Quad processor and 2GB memory */ 476 static const struct mx6_mmdc_calibration mx6q_2g_mmcd_calib = { 477 .p0_mpwldectrl0 = 0x00000000, 478 .p0_mpwldectrl1 = 0x00000000, 479 .p1_mpwldectrl0 = 0x00000000, 480 .p1_mpwldectrl1 = 0x00000000, 481 .p0_mpdgctrl0 = 0x0314031c, 482 .p0_mpdgctrl1 = 0x023e0304, 483 .p1_mpdgctrl0 = 0x03240330, 484 .p1_mpdgctrl1 = 0x03180260, 485 .p0_mprddlctl = 0x3630323c, 486 .p1_mprddlctl = 0x3436283a, 487 .p0_mpwrdlctl = 0x36344038, 488 .p1_mpwrdlctl = 0x422a423c, 489 }; 490 491 /* microSOM with Solo processor and 512MB memory */ 492 static const struct mx6_mmdc_calibration mx6dl_512m_mmcd_calib = { 493 .p0_mpwldectrl0 = 0x0045004D, 494 .p0_mpwldectrl1 = 0x003A0047, 495 .p0_mpdgctrl0 = 0x023C0224, 496 .p0_mpdgctrl1 = 0x02000220, 497 .p0_mprddlctl = 0x44444846, 498 .p0_mpwrdlctl = 0x32343032, 499 }; 500 501 /* microSOM with Dual lite processor and 1GB memory */ 502 static const struct mx6_mmdc_calibration mx6dl_1g_mmcd_calib = { 503 .p0_mpwldectrl0 = 0x0045004D, 504 .p0_mpwldectrl1 = 0x003A0047, 505 .p1_mpwldectrl0 = 0x001F001F, 506 .p1_mpwldectrl1 = 0x00210035, 507 .p0_mpdgctrl0 = 0x023C0224, 508 .p0_mpdgctrl1 = 0x02000220, 509 .p1_mpdgctrl0 = 0x02200220, 510 .p1_mpdgctrl1 = 0x02000220, 511 .p0_mprddlctl = 0x44444846, 512 .p1_mprddlctl = 0x4042463C, 513 .p0_mpwrdlctl = 0x32343032, 514 .p1_mpwrdlctl = 0x36363430, 515 }; 516 517 static struct mx6_ddr3_cfg mem_ddr_2g = { 518 .mem_speed = 1600, 519 .density = 2, 520 .width = 16, 521 .banks = 8, 522 .rowaddr = 14, 523 .coladdr = 10, 524 .pagesz = 2, 525 .trcd = 1375, 526 .trcmin = 4875, 527 .trasmin = 3500, 528 .SRT = 1, 529 }; 530 531 static struct mx6_ddr3_cfg mem_ddr_4g = { 532 .mem_speed = 1600, 533 .density = 4, 534 .width = 16, 535 .banks = 8, 536 .rowaddr = 15, 537 .coladdr = 10, 538 .pagesz = 2, 539 .trcd = 1375, 540 .trcmin = 4875, 541 .trasmin = 3500, 542 }; 543 544 static void ccgr_init(void) 545 { 546 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 547 548 writel(0x00C03F3F, &ccm->CCGR0); 549 writel(0x0030FC03, &ccm->CCGR1); 550 writel(0x0FFFC000, &ccm->CCGR2); 551 writel(0x3FF00000, &ccm->CCGR3); 552 writel(0x00FFF300, &ccm->CCGR4); 553 writel(0x0F0000C3, &ccm->CCGR5); 554 writel(0x000003FF, &ccm->CCGR6); 555 } 556 557 static void gpr_init(void) 558 { 559 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 560 561 /* enable AXI cache for VDOA/VPU/IPU */ 562 writel(0xF00000CF, &iomux->gpr[4]); 563 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 564 writel(0x007F007F, &iomux->gpr[6]); 565 writel(0x007F007F, &iomux->gpr[7]); 566 } 567 568 /* 569 * This section requires the differentiation between Solidrun mx6 boards, but 570 * for now, it will configure only for the mx6dual hummingboard version. 571 */ 572 static void spl_dram_init(int width) 573 { 574 struct mx6_ddr_sysinfo sysinfo = { 575 /* width of data bus: 0=16, 1=32, 2=64 */ 576 .dsize = width / 32, 577 /* config for full 4GB range so that get_mem_size() works */ 578 .cs_density = 32, /* 32Gb per CS */ 579 .ncs = 1, /* single chip select */ 580 .cs1_mirror = 0, 581 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 582 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 583 .walat = 1, /* Write additional latency */ 584 .ralat = 5, /* Read additional latency */ 585 .mif3_mode = 3, /* Command prediction working mode */ 586 .bi_on = 1, /* Bank interleaving enabled */ 587 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 588 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 589 }; 590 591 if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) 592 mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); 593 else 594 mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); 595 596 if (is_cpu_type(MXC_CPU_MX6D)) 597 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); 598 else if (is_cpu_type(MXC_CPU_MX6Q)) 599 mx6_dram_cfg(&sysinfo, &mx6q_2g_mmcd_calib, &mem_ddr_4g); 600 else if (is_cpu_type(MXC_CPU_MX6DL)) 601 mx6_dram_cfg(&sysinfo, &mx6q_1g_mmcd_calib, &mem_ddr_2g); 602 else if (is_cpu_type(MXC_CPU_MX6SOLO)) 603 mx6_dram_cfg(&sysinfo, &mx6dl_512m_mmcd_calib, &mem_ddr_2g); 604 } 605 606 void board_init_f(ulong dummy) 607 { 608 /* setup AIPS and disable watchdog */ 609 arch_cpu_init(); 610 611 ccgr_init(); 612 gpr_init(); 613 614 /* iomux and setup of i2c */ 615 board_early_init_f(); 616 617 /* setup GP timer */ 618 timer_init(); 619 620 /* UART clocks enabled and gd valid - init serial console */ 621 preloader_console_init(); 622 623 /* DDR initialization */ 624 if (is_cpu_type(MXC_CPU_MX6SOLO)) 625 spl_dram_init(32); 626 else 627 spl_dram_init(64); 628 629 /* Clear the BSS. */ 630 memset(__bss_start, 0, __bss_end - __bss_start); 631 632 /* load/boot image from boot device */ 633 board_init_r(NULL, 0); 634 } 635 #endif 636