1 /* 2 * (C) Copyright 2008 3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 4 * 5 * Copyright 2004 Freescale Semiconductor. 6 * (C) Copyright 2002,2003, Motorola Inc. 7 * Xianghua Xiao, (X.Xiao@motorola.com) 8 * 9 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30 #include <common.h> 31 #include <pci.h> 32 #include <asm/processor.h> 33 #include <asm/immap_85xx.h> 34 #include <ioports.h> 35 #include <flash.h> 36 #include <libfdt.h> 37 #include <fdt_support.h> 38 #include <asm/io.h> 39 40 DECLARE_GLOBAL_DATA_PTR; 41 42 extern flash_info_t flash_info[]; /* FLASH chips info */ 43 44 void local_bus_init (void); 45 ulong flash_get_size (ulong base, int banknum); 46 47 int checkboard (void) 48 { 49 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); 50 char *src; 51 int f; 52 char *s = getenv("serial#"); 53 54 puts("Board: Socrates"); 55 if (s != NULL) { 56 puts(", serial# "); 57 puts(s); 58 } 59 putc('\n'); 60 61 #ifdef CONFIG_PCI 62 /* Check the PCI_clk sel bit */ 63 if (in_be32(&gur->porpllsr) & (1<<15)) { 64 src = "SYSCLK"; 65 f = CONFIG_SYS_CLK_FREQ; 66 } else { 67 src = "PCI_CLK"; 68 f = CONFIG_PCI_CLK_FREQ; 69 } 70 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); 71 #else 72 printf ("PCI1: disabled\n"); 73 #endif 74 75 /* 76 * Initialize local bus. 77 */ 78 local_bus_init (); 79 80 return 0; 81 } 82 83 int misc_init_r (void) 84 { 85 volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR); 86 87 /* 88 * Adjust flash start and offset to detected values 89 */ 90 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; 91 gd->bd->bi_flashoffset = 0; 92 93 /* 94 * Check if boot FLASH isn't max size 95 */ 96 if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { 97 memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); 98 memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); 99 100 /* 101 * Re-check to get correct base address 102 */ 103 flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); 104 } 105 106 /* 107 * Check if only one FLASH bank is available 108 */ 109 if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { 110 memctl->or1 = 0; 111 memctl->br1 = 0; 112 113 /* 114 * Re-do flash protection upon new addresses 115 */ 116 flash_protect (FLAG_PROTECT_CLEAR, 117 gd->bd->bi_flashstart, 0xffffffff, 118 &flash_info[CFG_MAX_FLASH_BANKS - 1]); 119 120 /* Monitor protection ON by default */ 121 flash_protect (FLAG_PROTECT_SET, 122 CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, 123 &flash_info[CFG_MAX_FLASH_BANKS - 1]); 124 125 /* Environment protection ON by default */ 126 flash_protect (FLAG_PROTECT_SET, 127 CFG_ENV_ADDR, 128 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, 129 &flash_info[CFG_MAX_FLASH_BANKS - 1]); 130 131 /* Redundant environment protection ON by default */ 132 flash_protect (FLAG_PROTECT_SET, 133 CFG_ENV_ADDR_REDUND, 134 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, 135 &flash_info[CFG_MAX_FLASH_BANKS - 1]); 136 } 137 138 return 0; 139 } 140 141 /* 142 * Initialize Local Bus 143 */ 144 void local_bus_init (void) 145 { 146 147 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); 148 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); 149 150 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ 151 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ 152 ecm->eedr = 0xffffffff; /* Clear ecm errors */ 153 ecm->eeer = 0xffffffff; /* Enable ecm errors */ 154 155 } 156 157 #if defined(CONFIG_PCI) 158 /* 159 * Initialize PCI Devices, report devices found. 160 */ 161 162 #ifndef CONFIG_PCI_PNP 163 static struct pci_config_table pci_mpc85xxads_config_table[] = { 164 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 165 PCI_IDSEL_NUMBER, PCI_ANY_ID, 166 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 167 PCI_ENET0_MEMADDR, 168 PCI_COMMAND_MEMORY | 169 PCI_COMMAND_MASTER}}, 170 {} 171 }; 172 #endif 173 174 175 static struct pci_controller hose = { 176 #ifndef CONFIG_PCI_PNP 177 config_table:pci_mpc85xxads_config_table, 178 #endif 179 }; 180 181 #endif /* CONFIG_PCI */ 182 183 184 void pci_init_board (void) 185 { 186 #ifdef CONFIG_PCI 187 pci_mpc85xx_init (&hose); 188 #endif /* CONFIG_PCI */ 189 } 190 191 #ifdef CONFIG_BOARD_EARLY_INIT_R 192 int board_early_init_r (void) 193 { 194 #ifdef CONFIG_PS2MULT 195 ps2mult_early_init(); 196 #endif /* CONFIG_PS2MULT */ 197 return (0); 198 } 199 #endif /* CONFIG_BOARD_EARLY_INIT_R */ 200 201 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 202 void 203 ft_board_setup(void *blob, bd_t *bd) 204 { 205 u32 val[4]; 206 int rc; 207 208 ft_cpu_setup(blob, bd); 209 210 /* Fixup NOR mapping */ 211 val[0] = 0; /* chip select number */ 212 val[1] = 0; /* always 0 */ 213 val[2] = gd->bd->bi_flashstart; 214 val[3] = gd->bd->bi_flashsize; 215 216 rc = fdt_find_and_setprop(blob, "/localbus", "ranges", 217 val, sizeof(val), 1); 218 if (rc) 219 printf("Unable to update property NOR mapping, err=%s\n", 220 fdt_strerror(rc)); 221 } 222 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ 223