15d108ac8SSergei Poselenov /* 25d108ac8SSergei Poselenov * (C) Copyright 2008 35d108ac8SSergei Poselenov * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. 45d108ac8SSergei Poselenov * 55d108ac8SSergei Poselenov * Copyright 2008 Freescale Semiconductor, Inc. 65d108ac8SSergei Poselenov * 75d108ac8SSergei Poselenov * (C) Copyright 2000 85d108ac8SSergei Poselenov * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 95d108ac8SSergei Poselenov * 10*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 115d108ac8SSergei Poselenov */ 125d108ac8SSergei Poselenov 135d108ac8SSergei Poselenov #include <common.h> 145d108ac8SSergei Poselenov #include <asm/fsl_law.h> 155d108ac8SSergei Poselenov #include <asm/mmu.h> 165d108ac8SSergei Poselenov 175d108ac8SSergei Poselenov /* 185d108ac8SSergei Poselenov * LAW(Local Access Window) configuration: 195d108ac8SSergei Poselenov * 2059abd15bSSergei Poselenov * 0x0000_0000 0x2fff_ffff DDR 512M 215d108ac8SSergei Poselenov * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M 2259abd15bSSergei Poselenov * 0xc000_0000 0xc00f_ffff FPGA 1M 23e64987a8SAnatolij Gustschin * 0xc800_0000 0xcbff_ffff LIME 64M 2459abd15bSSergei Poselenov * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) 255d108ac8SSergei Poselenov * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M 2659abd15bSSergei Poselenov * 0xfc00_0000 0xffff_ffff FLASH 64M 275d108ac8SSergei Poselenov * 285d108ac8SSergei Poselenov * Notes: 295d108ac8SSergei Poselenov * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. 305d108ac8SSergei Poselenov * If flash is 8M at default position (last 8M), no LAW needed. 315d108ac8SSergei Poselenov */ 325d108ac8SSergei Poselenov 335d108ac8SSergei Poselenov struct law_entry law_table[] = { 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), 366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), 376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SYS_FPGA_BASE) 39002741aeSKumar Gala SET_LAW(CONFIG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC), 4059abd15bSSergei Poselenov #endif 41002741aeSKumar Gala SET_LAW(CONFIG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), 425d108ac8SSergei Poselenov }; 435d108ac8SSergei Poselenov 445d108ac8SSergei Poselenov int num_law_entries = ARRAY_SIZE(law_table); 45