xref: /rk3399_rockchip-uboot/board/sbc8349/pci.c (revision 326ea986ac150acdc7656d57fca647db80b50158)
191e25769SPaul Gortmaker /*
291e25769SPaul Gortmaker  * pci.c -- WindRiver SBC8349 PCI board support.
391e25769SPaul Gortmaker  * Copyright (c) 2006 Wind River Systems, Inc.
49993e196SKim Phillips  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
591e25769SPaul Gortmaker  *
691e25769SPaul Gortmaker  * Based on MPC8349 PCI support but w/o PIB related code.
791e25769SPaul Gortmaker  *
8*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
991e25769SPaul Gortmaker  */
1091e25769SPaul Gortmaker 
1191e25769SPaul Gortmaker #include <asm/mmu.h>
129993e196SKim Phillips #include <asm/io.h>
1391e25769SPaul Gortmaker #include <common.h>
149993e196SKim Phillips #include <mpc83xx.h>
1591e25769SPaul Gortmaker #include <pci.h>
1691e25769SPaul Gortmaker #include <i2c.h>
179993e196SKim Phillips #include <asm/fsl_i2c.h>
1891e25769SPaul Gortmaker 
1991e25769SPaul Gortmaker DECLARE_GLOBAL_DATA_PTR;
2091e25769SPaul Gortmaker 
219993e196SKim Phillips static struct pci_region pci1_regions[] = {
2291e25769SPaul Gortmaker 	{
239993e196SKim Phillips 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
249993e196SKim Phillips 		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
259993e196SKim Phillips 		size: CONFIG_SYS_PCI1_MEM_SIZE,
269993e196SKim Phillips 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
2791e25769SPaul Gortmaker 	},
2891e25769SPaul Gortmaker 	{
299993e196SKim Phillips 		bus_start: CONFIG_SYS_PCI1_IO_BASE,
309993e196SKim Phillips 		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
319993e196SKim Phillips 		size: CONFIG_SYS_PCI1_IO_SIZE,
329993e196SKim Phillips 		flags: PCI_REGION_IO
339993e196SKim Phillips 	},
349993e196SKim Phillips 	{
359993e196SKim Phillips 		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
369993e196SKim Phillips 		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
379993e196SKim Phillips 		size: CONFIG_SYS_PCI1_MMIO_SIZE,
389993e196SKim Phillips 		flags: PCI_REGION_MEM
399993e196SKim Phillips 	},
4091e25769SPaul Gortmaker };
4191e25769SPaul Gortmaker 
429993e196SKim Phillips /*
4391e25769SPaul Gortmaker  * pci_init_board()
4491e25769SPaul Gortmaker  *
4591e25769SPaul Gortmaker  * NOTICE: PCI2 is not supported. There is only one
4691e25769SPaul Gortmaker  * physical PCI slot on the board.
4791e25769SPaul Gortmaker  *
4891e25769SPaul Gortmaker  */
4991e25769SPaul Gortmaker void
pci_init_board(void)5091e25769SPaul Gortmaker pci_init_board(void)
5191e25769SPaul Gortmaker {
529993e196SKim Phillips 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
539993e196SKim Phillips 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
549993e196SKim Phillips 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
559993e196SKim Phillips 	struct pci_region *reg[] = { pci1_regions };
5691e25769SPaul Gortmaker 
579993e196SKim Phillips 	/* Enable all 8 PCI_CLK_OUTPUTS */
5891e25769SPaul Gortmaker 	clk->occr = 0xff000000;
5991e25769SPaul Gortmaker 	udelay(2000);
6091e25769SPaul Gortmaker 
619993e196SKim Phillips 	/* Configure PCI Local Access Windows */
626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
6391e25769SPaul Gortmaker 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
6491e25769SPaul Gortmaker 
656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD 	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
6691e25769SPaul Gortmaker 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
6791e25769SPaul Gortmaker 
689993e196SKim Phillips 	udelay(2000);
6991e25769SPaul Gortmaker 
706aa3d3bfSPeter Tyser 	mpc83xx_pci_init(1, reg);
7191e25769SPaul Gortmaker }
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