xref: /rk3399_rockchip-uboot/board/samsung/universal_c210/universal.c (revision 382bee57f19b4454e2015bc19a010bc2d0ab9337)
19e40808cSMinkyu Kang /*
29e40808cSMinkyu Kang  *  Copyright (C) 2010 Samsung Electronics
39e40808cSMinkyu Kang  *  Minkyu Kang <mk7.kang@samsung.com>
49e40808cSMinkyu Kang  *  Kyungmin Park <kyungmin.park@samsung.com>
59e40808cSMinkyu Kang  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
79e40808cSMinkyu Kang  */
89e40808cSMinkyu Kang 
99e40808cSMinkyu Kang #include <common.h>
10ff0fedd5SPiotr Wilczek #include <spi.h>
11d984b9f8SPiotr Wilczek #include <lcd.h>
129e40808cSMinkyu Kang #include <asm/io.h>
13ff0fedd5SPiotr Wilczek #include <asm/gpio.h>
149e40808cSMinkyu Kang #include <asm/arch/adc.h>
15ea7991b8SPiotr Wilczek #include <asm/arch/pinmux.h>
1611a44798SPiotr Wilczek #include <asm/arch/watchdog.h>
17d984b9f8SPiotr Wilczek #include <ld9040.h>
18c7336815SŁukasz Majewski #include <power/pmic.h>
193f41ffe4SPiotr Wilczek #include <usb.h>
205d5716eeSMarek Vasut #include <usb/dwc2_udc.h>
21ddc7e541SLukasz Majewski #include <asm/arch/cpu.h>
22c7336815SŁukasz Majewski #include <power/max8998_pmic.h>
233f41ffe4SPiotr Wilczek #include <libtizen.h>
2482b0a055SPrzemyslaw Marczak #include <samsung/misc.h>
253f41ffe4SPiotr Wilczek #include <usb_mass_storage.h>
26c62db35dSSimon Glass #include <asm/mach-types.h>
279e40808cSMinkyu Kang 
289e40808cSMinkyu Kang DECLARE_GLOBAL_DATA_PTR;
299e40808cSMinkyu Kang 
309e40808cSMinkyu Kang unsigned int board_rev;
31816d8b50SJaehoon Chung static int init_pmic_lcd(void);
329e40808cSMinkyu Kang 
get_board_rev(void)339e40808cSMinkyu Kang u32 get_board_rev(void)
349e40808cSMinkyu Kang {
359e40808cSMinkyu Kang 	return board_rev;
369e40808cSMinkyu Kang }
379e40808cSMinkyu Kang 
exynos_power_init(void)38816d8b50SJaehoon Chung int exynos_power_init(void)
39816d8b50SJaehoon Chung {
40816d8b50SJaehoon Chung 	return init_pmic_lcd();
41816d8b50SJaehoon Chung }
42816d8b50SJaehoon Chung 
get_hwrev(void)439e40808cSMinkyu Kang static int get_hwrev(void)
449e40808cSMinkyu Kang {
459e40808cSMinkyu Kang 	return board_rev & 0xFF;
469e40808cSMinkyu Kang }
479e40808cSMinkyu Kang 
get_adc_value(int channel)489e40808cSMinkyu Kang static unsigned short get_adc_value(int channel)
499e40808cSMinkyu Kang {
509e40808cSMinkyu Kang 	struct s5p_adc *adc = (struct s5p_adc *)samsung_get_base_adc();
519e40808cSMinkyu Kang 	unsigned short ret = 0;
529e40808cSMinkyu Kang 	unsigned int reg;
539e40808cSMinkyu Kang 	unsigned int loop = 0;
549e40808cSMinkyu Kang 
559e40808cSMinkyu Kang 	writel(channel & 0xF, &adc->adcmux);
569e40808cSMinkyu Kang 	writel((1 << 14) | (49 << 6), &adc->adccon);
579e40808cSMinkyu Kang 	writel(1000 & 0xffff, &adc->adcdly);
589e40808cSMinkyu Kang 	writel(readl(&adc->adccon) | (1 << 16), &adc->adccon); /* 12 bit */
599e40808cSMinkyu Kang 	udelay(10);
609e40808cSMinkyu Kang 	writel(readl(&adc->adccon) | (1 << 0), &adc->adccon); /* Enable */
619e40808cSMinkyu Kang 	udelay(10);
629e40808cSMinkyu Kang 
639e40808cSMinkyu Kang 	do {
649e40808cSMinkyu Kang 		udelay(1);
659e40808cSMinkyu Kang 		reg = readl(&adc->adccon);
669e40808cSMinkyu Kang 	} while (!(reg & (1 << 15)) && (loop++ < 1000));
679e40808cSMinkyu Kang 
689e40808cSMinkyu Kang 	ret = readl(&adc->adcdat0) & 0xFFF;
699e40808cSMinkyu Kang 
709e40808cSMinkyu Kang 	return ret;
719e40808cSMinkyu Kang }
729e40808cSMinkyu Kang 
adc_power_control(int on)734d86bf08SŁukasz Majewski static int adc_power_control(int on)
744d86bf08SŁukasz Majewski {
75816d8b50SJaehoon Chung 	struct udevice *dev;
764d86bf08SŁukasz Majewski 	int ret;
77816d8b50SJaehoon Chung 	u8 reg;
784d86bf08SŁukasz Majewski 
79816d8b50SJaehoon Chung 	ret = pmic_get("max8998-pmic", &dev);
80816d8b50SJaehoon Chung 	if (ret) {
81816d8b50SJaehoon Chung 		puts("Failed to get MAX8998!\n");
824d86bf08SŁukasz Majewski 		return ret;
83816d8b50SJaehoon Chung 	}
84816d8b50SJaehoon Chung 
85816d8b50SJaehoon Chung 	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
86816d8b50SJaehoon Chung 	if (on)
87816d8b50SJaehoon Chung 		reg |= MAX8998_LDO4;
88816d8b50SJaehoon Chung 	else
89816d8b50SJaehoon Chung 		reg &= ~MAX8998_LDO4;
90816d8b50SJaehoon Chung 
91816d8b50SJaehoon Chung 	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
92816d8b50SJaehoon Chung 	if (ret) {
93816d8b50SJaehoon Chung 		puts("MAX8998 LDO setting error\n");
94816d8b50SJaehoon Chung 		return -EINVAL;
95816d8b50SJaehoon Chung 	}
96816d8b50SJaehoon Chung 
97fc47cf9dSSimon Glass 	return 0;
984d86bf08SŁukasz Majewski }
994d86bf08SŁukasz Majewski 
get_hw_revision(void)1009e40808cSMinkyu Kang static unsigned int get_hw_revision(void)
1019e40808cSMinkyu Kang {
1029e40808cSMinkyu Kang 	int hwrev, mode0, mode1;
1039e40808cSMinkyu Kang 
1044d86bf08SŁukasz Majewski 	adc_power_control(1);
1054d86bf08SŁukasz Majewski 
1069e40808cSMinkyu Kang 	mode0 = get_adc_value(1);		/* HWREV_MODE0 */
1079e40808cSMinkyu Kang 	mode1 = get_adc_value(2);		/* HWREV_MODE1 */
1089e40808cSMinkyu Kang 
1099e40808cSMinkyu Kang 	/*
1109e40808cSMinkyu Kang 	 * XXX Always set the default hwrev as the latest board
1119e40808cSMinkyu Kang 	 * ADC = (voltage) / 3.3 * 4096
1129e40808cSMinkyu Kang 	 */
1139e40808cSMinkyu Kang 	hwrev = 3;
1149e40808cSMinkyu Kang 
1159e40808cSMinkyu Kang #define IS_RANGE(x, min, max)	((x) > (min) && (x) < (max))
1169e40808cSMinkyu Kang 	if (IS_RANGE(mode0, 80, 200) && IS_RANGE(mode1, 80, 200))
1179e40808cSMinkyu Kang 		hwrev = 0x0;		/* 0.01V	0.01V */
1189e40808cSMinkyu Kang 	if (IS_RANGE(mode0, 750, 1000) && IS_RANGE(mode1, 80, 200))
1199e40808cSMinkyu Kang 		hwrev = 0x1;		/* 610mV	0.01V */
1209e40808cSMinkyu Kang 	if (IS_RANGE(mode0, 1300, 1700) && IS_RANGE(mode1, 80, 200))
1219e40808cSMinkyu Kang 		hwrev = 0x2;		/* 1.16V	0.01V */
1229e40808cSMinkyu Kang 	if (IS_RANGE(mode0, 2000, 2400) && IS_RANGE(mode1, 80, 200))
1239e40808cSMinkyu Kang 		hwrev = 0x3;		/* 1.79V	0.01V */
1249e40808cSMinkyu Kang #undef IS_RANGE
1259e40808cSMinkyu Kang 
1269e40808cSMinkyu Kang 	debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev);
1279e40808cSMinkyu Kang 
1284d86bf08SŁukasz Majewski 	adc_power_control(0);
1294d86bf08SŁukasz Majewski 
1309e40808cSMinkyu Kang 	return hwrev;
1319e40808cSMinkyu Kang }
1329e40808cSMinkyu Kang 
check_hw_revision(void)1339e40808cSMinkyu Kang static void check_hw_revision(void)
1349e40808cSMinkyu Kang {
1359e40808cSMinkyu Kang 	int hwrev;
1369e40808cSMinkyu Kang 
1379e40808cSMinkyu Kang 	hwrev = get_hw_revision();
1389e40808cSMinkyu Kang 
1399e40808cSMinkyu Kang 	board_rev |= hwrev;
1409e40808cSMinkyu Kang }
1419e40808cSMinkyu Kang 
142ddc7e541SLukasz Majewski #ifdef CONFIG_USB_GADGET
s5pc210_phy_control(int on)143ddc7e541SLukasz Majewski static int s5pc210_phy_control(int on)
144ddc7e541SLukasz Majewski {
145816d8b50SJaehoon Chung 	struct udevice *dev;
146816d8b50SJaehoon Chung 	int ret;
147816d8b50SJaehoon Chung 	u8 reg;
148ddc7e541SLukasz Majewski 
149816d8b50SJaehoon Chung 	ret = pmic_get("max8998-pmic", &dev);
150816d8b50SJaehoon Chung 	if (ret) {
151816d8b50SJaehoon Chung 		puts("Failed to get MAX8998!\n");
152816d8b50SJaehoon Chung 		return ret;
153816d8b50SJaehoon Chung 	}
154ddc7e541SLukasz Majewski 
155ddc7e541SLukasz Majewski 	if (on) {
156816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
157816d8b50SJaehoon Chung 		reg |= MAX8998_SAFEOUT1;
158816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev,
159816d8b50SJaehoon Chung 			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
160816d8b50SJaehoon Chung 
161816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
162816d8b50SJaehoon Chung 		reg |= MAX8998_LDO3;
163816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
164816d8b50SJaehoon Chung 
165816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
166816d8b50SJaehoon Chung 		reg |= MAX8998_LDO8;
167816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
168ddc7e541SLukasz Majewski 
169ddc7e541SLukasz Majewski 	} else {
170816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
171816d8b50SJaehoon Chung 		reg &= ~MAX8998_LDO8;
172816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
173816d8b50SJaehoon Chung 
174816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_ONOFF1);
175816d8b50SJaehoon Chung 		reg &= ~MAX8998_LDO3;
176816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev, MAX8998_REG_ONOFF1, reg);
177816d8b50SJaehoon Chung 
178816d8b50SJaehoon Chung 		reg = pmic_reg_read(dev, MAX8998_REG_BUCK_ACTIVE_DISCHARGE3);
179816d8b50SJaehoon Chung 		reg &= ~MAX8998_SAFEOUT1;
180816d8b50SJaehoon Chung 		ret |= pmic_reg_write(dev,
181816d8b50SJaehoon Chung 			MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, reg);
182ddc7e541SLukasz Majewski 	}
183ddc7e541SLukasz Majewski 
184ddc7e541SLukasz Majewski 	if (ret) {
185ddc7e541SLukasz Majewski 		puts("MAX8998 LDO setting error!\n");
186816d8b50SJaehoon Chung 		return -EINVAL;
187ddc7e541SLukasz Majewski 	}
188816d8b50SJaehoon Chung 
189ddc7e541SLukasz Majewski 	return 0;
190ddc7e541SLukasz Majewski }
191ddc7e541SLukasz Majewski 
192c0982871SMarek Vasut struct dwc2_plat_otg_data s5pc210_otg_data = {
193ddc7e541SLukasz Majewski 	.phy_control = s5pc210_phy_control,
194ddc7e541SLukasz Majewski 	.regs_phy = EXYNOS4_USBPHY_BASE,
195ddc7e541SLukasz Majewski 	.regs_otg = EXYNOS4_USBOTG_BASE,
196ddc7e541SLukasz Majewski 	.usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL,
197ddc7e541SLukasz Majewski 	.usb_flags = PHY0_SLEEP,
198ddc7e541SLukasz Majewski };
199ddc7e541SLukasz Majewski #endif
20011a44798SPiotr Wilczek 
board_usb_init(int index,enum usb_init_type init)2013f41ffe4SPiotr Wilczek int board_usb_init(int index, enum usb_init_type init)
2023f41ffe4SPiotr Wilczek {
2033f41ffe4SPiotr Wilczek 	debug("USB_udc_probe\n");
204a4bb9b36SMarek Vasut 	return dwc2_udc_probe(&s5pc210_otg_data);
2053f41ffe4SPiotr Wilczek }
2063f41ffe4SPiotr Wilczek 
exynos_early_init_f(void)2073f41ffe4SPiotr Wilczek int exynos_early_init_f(void)
20811a44798SPiotr Wilczek {
20911a44798SPiotr Wilczek 	wdt_stop();
21011a44798SPiotr Wilczek 
21111a44798SPiotr Wilczek 	return 0;
21211a44798SPiotr Wilczek }
213ff0fedd5SPiotr Wilczek 
init_pmic_lcd(void)214816d8b50SJaehoon Chung static int init_pmic_lcd(void)
215d984b9f8SPiotr Wilczek {
216816d8b50SJaehoon Chung 	struct udevice *dev;
217d984b9f8SPiotr Wilczek 	unsigned char val;
218d984b9f8SPiotr Wilczek 	int ret = 0;
219d984b9f8SPiotr Wilczek 
220816d8b50SJaehoon Chung 	ret = pmic_get("max8998-pmic", &dev);
221816d8b50SJaehoon Chung 	if (ret) {
222816d8b50SJaehoon Chung 		puts("Failed to get MAX8998 for init_pmic_lcd()!\n");
223816d8b50SJaehoon Chung 		return ret;
224816d8b50SJaehoon Chung 	}
225d984b9f8SPiotr Wilczek 
226d984b9f8SPiotr Wilczek 	/* LDO7 1.8V */
227d984b9f8SPiotr Wilczek 	val = 0x02; /* (1800 - 1600) / 100; */
228816d8b50SJaehoon Chung 	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO7, val);
229d984b9f8SPiotr Wilczek 
230d984b9f8SPiotr Wilczek 	/* LDO17 3.0V */
231d984b9f8SPiotr Wilczek 	val = 0xe; /* (3000 - 1600) / 100; */
232816d8b50SJaehoon Chung 	ret |= pmic_reg_write(dev,  MAX8998_REG_LDO17, val);
233d984b9f8SPiotr Wilczek 
234d984b9f8SPiotr Wilczek 	/* Disable unneeded regulators */
235d984b9f8SPiotr Wilczek 	/*
236d984b9f8SPiotr Wilczek 	 * ONOFF1
237d984b9f8SPiotr Wilczek 	 * Buck1 ON, Buck2 OFF, Buck3 ON, Buck4 ON
238d984b9f8SPiotr Wilczek 	 * LDO2 ON, LDO3 OFF, LDO4 OFF, LDO5 ON
239d984b9f8SPiotr Wilczek 	 */
240d984b9f8SPiotr Wilczek 	val = 0xB9;
241816d8b50SJaehoon Chung 	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF1, val);
242d984b9f8SPiotr Wilczek 
243d984b9f8SPiotr Wilczek 	/* ONOFF2
244d984b9f8SPiotr Wilczek 	 * LDO6 OFF, LDO7 ON, LDO8 OFF, LDO9 ON,
245d984b9f8SPiotr Wilczek 	 * LDO10 OFF, LDO11 OFF, LDO12 OFF, LDO13 OFF
246d984b9f8SPiotr Wilczek 	 */
247d984b9f8SPiotr Wilczek 	val = 0x50;
248816d8b50SJaehoon Chung 	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF2, val);
249d984b9f8SPiotr Wilczek 
250d984b9f8SPiotr Wilczek 	/* ONOFF3
251d984b9f8SPiotr Wilczek 	 * LDO14 OFF, LDO15 OFF, LGO16 OFF, LDO17 OFF
252d984b9f8SPiotr Wilczek 	 * EPWRHOLD OFF, EBATTMON OFF, ELBCNFG2 OFF, ELBCNFG1 OFF
253d984b9f8SPiotr Wilczek 	 */
254d984b9f8SPiotr Wilczek 	val = 0x00;
255816d8b50SJaehoon Chung 	ret |= pmic_reg_write(dev,  MAX8998_REG_ONOFF3, val);
256d984b9f8SPiotr Wilczek 
257816d8b50SJaehoon Chung 	if (ret) {
258d984b9f8SPiotr Wilczek 		puts("LCD pmic initialisation error!\n");
259816d8b50SJaehoon Chung 		return -EINVAL;
260d984b9f8SPiotr Wilczek 	}
261816d8b50SJaehoon Chung 
262816d8b50SJaehoon Chung 	return 0;
263816d8b50SJaehoon Chung }
264d984b9f8SPiotr Wilczek 
exynos_cfg_lcd_gpio(void)26529fd5704SAjay Kumar void exynos_cfg_lcd_gpio(void)
266d984b9f8SPiotr Wilczek {
267d984b9f8SPiotr Wilczek 	unsigned int i, f3_end = 4;
268d984b9f8SPiotr Wilczek 
269d984b9f8SPiotr Wilczek 	for (i = 0; i < 8; i++) {
270d984b9f8SPiotr Wilczek 		/* set GPF0,1,2[0:7] for RGB Interface and Data lines (32bit) */
271f6ae1ca0SAkshay Saraswat 		gpio_cfg_pin(EXYNOS4_GPIO_F00 + i, S5P_GPIO_FUNC(2));
272f6ae1ca0SAkshay Saraswat 		gpio_cfg_pin(EXYNOS4_GPIO_F10 + i, S5P_GPIO_FUNC(2));
273f6ae1ca0SAkshay Saraswat 		gpio_cfg_pin(EXYNOS4_GPIO_F20 + i, S5P_GPIO_FUNC(2));
274d984b9f8SPiotr Wilczek 		/* pull-up/down disable */
275f6ae1ca0SAkshay Saraswat 		gpio_set_pull(EXYNOS4_GPIO_F00 + i, S5P_GPIO_PULL_NONE);
276f6ae1ca0SAkshay Saraswat 		gpio_set_pull(EXYNOS4_GPIO_F10 + i, S5P_GPIO_PULL_NONE);
277f6ae1ca0SAkshay Saraswat 		gpio_set_pull(EXYNOS4_GPIO_F20 + i, S5P_GPIO_PULL_NONE);
278d984b9f8SPiotr Wilczek 
279d984b9f8SPiotr Wilczek 		/* drive strength to max (24bit) */
280f6ae1ca0SAkshay Saraswat 		gpio_set_drv(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_4X);
281f6ae1ca0SAkshay Saraswat 		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
282f6ae1ca0SAkshay Saraswat 		gpio_set_drv(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_4X);
283f6ae1ca0SAkshay Saraswat 		gpio_set_rate(EXYNOS4_GPIO_F10 + i, S5P_GPIO_DRV_SLOW);
284f6ae1ca0SAkshay Saraswat 		gpio_set_drv(EXYNOS4_GPIO_F20 + i, S5P_GPIO_DRV_4X);
285f6ae1ca0SAkshay Saraswat 		gpio_set_rate(EXYNOS4_GPIO_F00 + i, S5P_GPIO_DRV_SLOW);
286d984b9f8SPiotr Wilczek 	}
287d984b9f8SPiotr Wilczek 
288f6ae1ca0SAkshay Saraswat 	for (i = EXYNOS4_GPIO_F30; i < (EXYNOS4_GPIO_F30 + f3_end); i++) {
289d984b9f8SPiotr Wilczek 		/* set GPF3[0:3] for RGB Interface and Data lines (32bit) */
290f6ae1ca0SAkshay Saraswat 		gpio_cfg_pin(i, S5P_GPIO_FUNC(2));
291d984b9f8SPiotr Wilczek 		/* pull-up/down disable */
292f6ae1ca0SAkshay Saraswat 		gpio_set_pull(i, S5P_GPIO_PULL_NONE);
293d984b9f8SPiotr Wilczek 		/* drive strength to max (24bit) */
294f6ae1ca0SAkshay Saraswat 		gpio_set_drv(i, S5P_GPIO_DRV_4X);
295f6ae1ca0SAkshay Saraswat 		gpio_set_rate(i, S5P_GPIO_DRV_SLOW);
296d984b9f8SPiotr Wilczek 	}
297d984b9f8SPiotr Wilczek 
298d984b9f8SPiotr Wilczek 	/* gpio pad configuration for LCD reset. */
2997f196101SSimon Glass 	gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset");
300f6ae1ca0SAkshay Saraswat 	gpio_cfg_pin(EXYNOS4_GPIO_Y45, S5P_GPIO_OUTPUT);
301d984b9f8SPiotr Wilczek }
302d984b9f8SPiotr Wilczek 
mipi_power(void)3033f41ffe4SPiotr Wilczek int mipi_power(void)
3043f41ffe4SPiotr Wilczek {
3053f41ffe4SPiotr Wilczek 	return 0;
3063f41ffe4SPiotr Wilczek }
3073f41ffe4SPiotr Wilczek 
exynos_reset_lcd(void)30829fd5704SAjay Kumar void exynos_reset_lcd(void)
309d984b9f8SPiotr Wilczek {
310f6ae1ca0SAkshay Saraswat 	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
311d984b9f8SPiotr Wilczek 	udelay(10000);
312f6ae1ca0SAkshay Saraswat 	gpio_set_value(EXYNOS4_GPIO_Y45, 0);
313d984b9f8SPiotr Wilczek 	udelay(10000);
314f6ae1ca0SAkshay Saraswat 	gpio_set_value(EXYNOS4_GPIO_Y45, 1);
315d984b9f8SPiotr Wilczek 	udelay(100);
316d984b9f8SPiotr Wilczek }
317d984b9f8SPiotr Wilczek 
exynos_lcd_power_on(void)31829fd5704SAjay Kumar void exynos_lcd_power_on(void)
319d984b9f8SPiotr Wilczek {
320816d8b50SJaehoon Chung 	struct udevice *dev;
321816d8b50SJaehoon Chung 	int ret;
322816d8b50SJaehoon Chung 	u8 reg;
323d984b9f8SPiotr Wilczek 
324816d8b50SJaehoon Chung 	ret = pmic_get("max8998-pmic", &dev);
325816d8b50SJaehoon Chung 	if (ret) {
326816d8b50SJaehoon Chung 		puts("Failed to get MAX8998!\n");
327fbef8e6eSMinkyu Kang 		return;
328816d8b50SJaehoon Chung 	}
329fbef8e6eSMinkyu Kang 
330816d8b50SJaehoon Chung 	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF3);
331816d8b50SJaehoon Chung 	reg |= MAX8998_LDO17;
332816d8b50SJaehoon Chung 	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF3, reg);
333816d8b50SJaehoon Chung 	if (ret) {
334816d8b50SJaehoon Chung 		puts("MAX8998 LDO setting error\n");
335d984b9f8SPiotr Wilczek 		return;
336816d8b50SJaehoon Chung 	}
337d984b9f8SPiotr Wilczek 
338816d8b50SJaehoon Chung 	reg = pmic_reg_read(dev, MAX8998_REG_ONOFF2);
339816d8b50SJaehoon Chung 	reg |= MAX8998_LDO7;
340816d8b50SJaehoon Chung 	ret = pmic_reg_write(dev, MAX8998_REG_ONOFF2, reg);
341816d8b50SJaehoon Chung 	if (ret) {
342816d8b50SJaehoon Chung 		puts("MAX8998 LDO setting error\n");
343816d8b50SJaehoon Chung 		return;
344816d8b50SJaehoon Chung 	}
345d984b9f8SPiotr Wilczek }
346d984b9f8SPiotr Wilczek 
exynos_cfg_ldo(void)34729fd5704SAjay Kumar void exynos_cfg_ldo(void)
34829fd5704SAjay Kumar {
34929fd5704SAjay Kumar 	ld9040_cfg_ldo();
35029fd5704SAjay Kumar }
35129fd5704SAjay Kumar 
exynos_enable_ldo(unsigned int onoff)35229fd5704SAjay Kumar void exynos_enable_ldo(unsigned int onoff)
35329fd5704SAjay Kumar {
35429fd5704SAjay Kumar 	ld9040_enable_ldo(onoff);
35529fd5704SAjay Kumar }
35629fd5704SAjay Kumar 
exynos_init(void)3573f41ffe4SPiotr Wilczek int exynos_init(void)
358ff0fedd5SPiotr Wilczek {
359ff0fedd5SPiotr Wilczek 	gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
3603f41ffe4SPiotr Wilczek 
3613f41ffe4SPiotr Wilczek 	switch (get_hwrev()) {
3623f41ffe4SPiotr Wilczek 	case 0:
3633f41ffe4SPiotr Wilczek 		/*
3643f41ffe4SPiotr Wilczek 		 * Set the low to enable LDO_EN
3653f41ffe4SPiotr Wilczek 		 * But when you use the test board for eMMC booting
3663f41ffe4SPiotr Wilczek 		 * you should set it HIGH since it removes the inverter
3673f41ffe4SPiotr Wilczek 		 */
3683f41ffe4SPiotr Wilczek 		/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
3697f196101SSimon Glass 		gpio_request(EXYNOS4_GPIO_E36, "ldo_en");
370f6ae1ca0SAkshay Saraswat 		gpio_direction_output(EXYNOS4_GPIO_E36, 0);
3713f41ffe4SPiotr Wilczek 		break;
3723f41ffe4SPiotr Wilczek 	default:
3733f41ffe4SPiotr Wilczek 		/*
3743f41ffe4SPiotr Wilczek 		 * Default reset state is High and there's no inverter
3753f41ffe4SPiotr Wilczek 		 * But set it as HIGH to ensure
3763f41ffe4SPiotr Wilczek 		 */
3773f41ffe4SPiotr Wilczek 		/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
3787f196101SSimon Glass 		gpio_request(EXYNOS4_GPIO_E13, "massmemory_en");
379f6ae1ca0SAkshay Saraswat 		gpio_direction_output(EXYNOS4_GPIO_E13, 1);
3803f41ffe4SPiotr Wilczek 		break;
3813f41ffe4SPiotr Wilczek 	}
382ff0fedd5SPiotr Wilczek 
383ff0fedd5SPiotr Wilczek 	check_hw_revision();
384ff0fedd5SPiotr Wilczek 	printf("HW Revision:\t0x%x\n", board_rev);
385ff0fedd5SPiotr Wilczek 
386ff0fedd5SPiotr Wilczek 	return 0;
387ff0fedd5SPiotr Wilczek }
388679549d1SPrzemyslaw Marczak 
389ea743e65SSimon Glass #ifdef CONFIG_LCD
exynos_lcd_misc_init(vidinfo_t * vid)3903f41ffe4SPiotr Wilczek void exynos_lcd_misc_init(vidinfo_t *vid)
391679549d1SPrzemyslaw Marczak {
3923f41ffe4SPiotr Wilczek #ifdef CONFIG_TIZEN
3933f41ffe4SPiotr Wilczek 	get_tizen_logo_info(vid);
394815a6072SPiotr Wilczek #endif
3953f41ffe4SPiotr Wilczek 
3963f41ffe4SPiotr Wilczek 	/* for LD9040. */
3973f41ffe4SPiotr Wilczek 	vid->pclk_name = 1;	/* MPLL */
3983f41ffe4SPiotr Wilczek 	vid->sclk_div = 1;
3993f41ffe4SPiotr Wilczek 
400*382bee57SSimon Glass 	env_set("lcdinfo", "lcd=ld9040");
401679549d1SPrzemyslaw Marczak }
402ea743e65SSimon Glass #endif
403