1 /* 2 * Copyright (C) 2011 Samsung Electronics 3 * Heungjun Kim <riverful.kim@samsung.com> 4 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Donghwa Lee <dh09.lee@samsung.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <lcd.h> 12 #include <asm/io.h> 13 #include <asm/gpio.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/arch/pinmux.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/mipi_dsim.h> 18 #include <asm/arch/watchdog.h> 19 #include <asm/arch/power.h> 20 #include <power/pmic.h> 21 #include <usb/dwc2_udc.h> 22 #include <power/max8997_pmic.h> 23 #include <power/max8997_muic.h> 24 #include <power/battery.h> 25 #include <power/max17042_fg.h> 26 #include <libtizen.h> 27 #include <usb.h> 28 #include <usb_mass_storage.h> 29 30 #include "setup.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 unsigned int board_rev; 35 36 #ifdef CONFIG_REVISION_TAG 37 u32 get_board_rev(void) 38 { 39 return board_rev; 40 } 41 #endif 42 43 static void check_hw_revision(void); 44 struct dwc2_plat_otg_data s5pc210_otg_data; 45 46 int exynos_init(void) 47 { 48 check_hw_revision(); 49 printf("HW Revision:\t0x%x\n", board_rev); 50 51 return 0; 52 } 53 54 void i2c_init_board(void) 55 { 56 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 57 int err; 58 59 /* I2C_8 -> FG */ 60 gpio_request(EXYNOS4_GPIO_Y40, "i2c_clk"); 61 gpio_request(EXYNOS4_GPIO_Y41, "i2c_data"); 62 gpio_direction_output(EXYNOS4_GPIO_Y40, 1); 63 gpio_direction_output(EXYNOS4_GPIO_Y41, 1); 64 #endif 65 } 66 67 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 68 static void trats_low_power_mode(void) 69 { 70 struct exynos4_clock *clk = 71 (struct exynos4_clock *)samsung_get_base_clock(); 72 struct exynos4_power *pwr = 73 (struct exynos4_power *)samsung_get_base_power(); 74 75 /* Power down CORE1 */ 76 /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ 77 writel(0x0, &pwr->arm_core1_configuration); 78 79 /* Change the APLL frequency */ 80 /* ENABLE (1 enable) | LOCKED (1 locked) */ 81 /* [31] | [29] */ 82 /* FSEL | MDIV | PDIV | SDIV */ 83 /* [27] | [25:16] | [13:8] | [2:0] */ 84 writel(0xa0c80604, &clk->apll_con0); 85 86 /* Change CPU0 clock divider */ 87 /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ 88 /* [30:28] | [26:24] | [22:20] | [18:16] */ 89 /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ 90 /* [14:12] | [10:8] | [6:4] | [2:0] */ 91 writel(0x00000100, &clk->div_cpu0); 92 93 /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ 94 while (readl(&clk->div_stat_cpu0) & 0x1111111) 95 continue; 96 97 /* Change clock divider ratio for DMC */ 98 /* DMCP_RATIO | DMCD_RATIO */ 99 /* [22:20] | [18:16] */ 100 /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ 101 /* [14:12] | [10:8] | [6:4] | [2:0] */ 102 writel(0x13113117, &clk->div_dmc0); 103 104 /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ 105 while (readl(&clk->div_stat_dmc0) & 0x11111111) 106 continue; 107 108 /* Turn off unnecessary power domains */ 109 writel(0x0, &pwr->xxti_configuration); /* XXTI */ 110 writel(0x0, &pwr->cam_configuration); /* CAM */ 111 writel(0x0, &pwr->tv_configuration); /* TV */ 112 writel(0x0, &pwr->mfc_configuration); /* MFC */ 113 writel(0x0, &pwr->g3d_configuration); /* G3D */ 114 writel(0x0, &pwr->gps_configuration); /* GPS */ 115 writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ 116 117 /* Turn off unnecessary clocks */ 118 writel(0x0, &clk->gate_ip_cam); /* CAM */ 119 writel(0x0, &clk->gate_ip_tv); /* TV */ 120 writel(0x0, &clk->gate_ip_mfc); /* MFC */ 121 writel(0x0, &clk->gate_ip_g3d); /* G3D */ 122 writel(0x0, &clk->gate_ip_image); /* IMAGE */ 123 writel(0x0, &clk->gate_ip_gps); /* GPS */ 124 } 125 #endif 126 127 int exynos_power_init(void) 128 { 129 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 130 int chrg, ret; 131 struct power_battery *pb; 132 struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; 133 134 /* 135 * For PMIC/MUIC the I2C bus is named as I2C5, but it is connected 136 * to logical I2C adapter 0 137 * 138 * The FUEL_GAUGE is marked as I2C9 on the schematic, but connected 139 * to logical I2C adapter 1 140 */ 141 ret = power_fg_init(I2C_9); 142 ret |= power_muic_init(I2C_5); 143 ret |= power_bat_init(0); 144 if (ret) 145 return ret; 146 147 p_fg = pmic_get("MAX17042_FG"); 148 if (!p_fg) { 149 puts("MAX17042_FG: Not found\n"); 150 return -ENODEV; 151 } 152 153 p_chrg = pmic_get("MAX8997_PMIC"); 154 if (!p_chrg) { 155 puts("MAX8997_PMIC: Not found\n"); 156 return -ENODEV; 157 } 158 159 p_muic = pmic_get("MAX8997_MUIC"); 160 if (!p_muic) { 161 puts("MAX8997_MUIC: Not found\n"); 162 return -ENODEV; 163 } 164 165 p_bat = pmic_get("BAT_TRATS"); 166 if (!p_bat) { 167 puts("BAT_TRATS: Not found\n"); 168 return -ENODEV; 169 } 170 171 p_fg->parent = p_bat; 172 p_chrg->parent = p_bat; 173 p_muic->parent = p_bat; 174 175 p_bat->low_power_mode = trats_low_power_mode; 176 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 177 178 pb = p_bat->pbat; 179 chrg = p_muic->chrg->chrg_type(p_muic); 180 debug("CHARGER TYPE: %d\n", chrg); 181 182 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 183 puts("No battery detected\n"); 184 return 0; 185 } 186 187 p_fg->fg->fg_battery_check(p_fg, p_bat); 188 189 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 190 puts("CHARGE Battery !\n"); 191 #endif 192 193 return 0; 194 } 195 196 static unsigned int get_hw_revision(void) 197 { 198 int hwrev = 0; 199 char str[10]; 200 int i; 201 202 /* hw_rev[3:0] == GPE1[3:0] */ 203 for (i = 0; i < 4; i++) { 204 int pin = i + EXYNOS4_GPIO_E10; 205 206 sprintf(str, "hw_rev%d", i); 207 gpio_request(pin, str); 208 gpio_cfg_pin(pin, S5P_GPIO_INPUT); 209 gpio_set_pull(pin, S5P_GPIO_PULL_NONE); 210 } 211 212 udelay(1); 213 214 for (i = 0; i < 4; i++) 215 hwrev |= (gpio_get_value(EXYNOS4_GPIO_E10 + i) << i); 216 217 debug("hwrev 0x%x\n", hwrev); 218 219 return hwrev; 220 } 221 222 static void check_hw_revision(void) 223 { 224 int hwrev; 225 226 hwrev = get_hw_revision(); 227 228 board_rev |= hwrev; 229 } 230 231 232 #ifdef CONFIG_USB_GADGET 233 static int s5pc210_phy_control(int on) 234 { 235 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 236 int ret = 0; 237 u32 val = 0; 238 struct pmic *p = pmic_get("MAX8997_PMIC"); 239 if (!p) 240 return -ENODEV; 241 242 if (pmic_probe(p)) 243 return -1; 244 245 if (on) { 246 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 247 ENSAFEOUT1, LDO_ON); 248 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 249 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO | val); 250 251 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 252 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO | val); 253 } else { 254 ret |= pmic_reg_read(p, MAX8997_REG_LDO8CTRL, &val); 255 ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO | val); 256 257 ret |= pmic_reg_read(p, MAX8997_REG_LDO3CTRL, &val); 258 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO | val); 259 ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, 260 ENSAFEOUT1, LDO_OFF); 261 } 262 263 if (ret) { 264 puts("MAX8997 LDO setting error!\n"); 265 return -1; 266 } 267 #endif 268 269 return 0; 270 } 271 272 struct dwc2_plat_otg_data s5pc210_otg_data = { 273 .phy_control = s5pc210_phy_control, 274 .regs_phy = EXYNOS4_USBPHY_BASE, 275 .regs_otg = EXYNOS4_USBOTG_BASE, 276 .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, 277 .usb_flags = PHY0_SLEEP, 278 }; 279 280 int board_usb_init(int index, enum usb_init_type init) 281 { 282 debug("USB_udc_probe\n"); 283 return dwc2_udc_probe(&s5pc210_otg_data); 284 } 285 286 int g_dnl_board_usb_cable_connected(void) 287 { 288 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 289 struct pmic *muic = pmic_get("MAX8997_MUIC"); 290 if (!muic) 291 return 0; 292 293 return !!muic->chrg->chrg_type(muic); 294 #else 295 return false; 296 #endif 297 298 } 299 #endif 300 301 static void pmic_reset(void) 302 { 303 gpio_direction_output(EXYNOS4_GPIO_X07, 1); 304 gpio_set_pull(EXYNOS4_GPIO_X27, S5P_GPIO_PULL_NONE); 305 } 306 307 static void board_clock_init(void) 308 { 309 struct exynos4_clock *clk = 310 (struct exynos4_clock *)samsung_get_base_clock(); 311 312 writel(CLK_SRC_CPU_VAL, (unsigned int)&clk->src_cpu); 313 writel(CLK_SRC_TOP0_VAL, (unsigned int)&clk->src_top0); 314 writel(CLK_SRC_FSYS_VAL, (unsigned int)&clk->src_fsys); 315 writel(CLK_SRC_PERIL0_VAL, (unsigned int)&clk->src_peril0); 316 317 writel(CLK_DIV_CPU0_VAL, (unsigned int)&clk->div_cpu0); 318 writel(CLK_DIV_CPU1_VAL, (unsigned int)&clk->div_cpu1); 319 writel(CLK_DIV_DMC0_VAL, (unsigned int)&clk->div_dmc0); 320 writel(CLK_DIV_DMC1_VAL, (unsigned int)&clk->div_dmc1); 321 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); 322 writel(CLK_DIV_RIGHTBUS_VAL, (unsigned int)&clk->div_rightbus); 323 writel(CLK_DIV_TOP_VAL, (unsigned int)&clk->div_top); 324 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); 325 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); 326 writel(CLK_DIV_FSYS3_VAL, (unsigned int)&clk->div_fsys3); 327 writel(CLK_DIV_PERIL0_VAL, (unsigned int)&clk->div_peril0); 328 writel(CLK_DIV_PERIL3_VAL, (unsigned int)&clk->div_peril3); 329 330 writel(PLL_LOCKTIME, (unsigned int)&clk->apll_lock); 331 writel(PLL_LOCKTIME, (unsigned int)&clk->mpll_lock); 332 writel(PLL_LOCKTIME, (unsigned int)&clk->epll_lock); 333 writel(PLL_LOCKTIME, (unsigned int)&clk->vpll_lock); 334 writel(APLL_CON1_VAL, (unsigned int)&clk->apll_con1); 335 writel(APLL_CON0_VAL, (unsigned int)&clk->apll_con0); 336 writel(MPLL_CON1_VAL, (unsigned int)&clk->mpll_con1); 337 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); 338 writel(EPLL_CON1_VAL, (unsigned int)&clk->epll_con1); 339 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); 340 writel(VPLL_CON1_VAL, (unsigned int)&clk->vpll_con1); 341 writel(VPLL_CON0_VAL, (unsigned int)&clk->vpll_con0); 342 343 writel(CLK_GATE_IP_CAM_VAL, (unsigned int)&clk->gate_ip_cam); 344 writel(CLK_GATE_IP_VP_VAL, (unsigned int)&clk->gate_ip_tv); 345 writel(CLK_GATE_IP_MFC_VAL, (unsigned int)&clk->gate_ip_mfc); 346 writel(CLK_GATE_IP_G3D_VAL, (unsigned int)&clk->gate_ip_g3d); 347 writel(CLK_GATE_IP_IMAGE_VAL, (unsigned int)&clk->gate_ip_image); 348 writel(CLK_GATE_IP_LCD0_VAL, (unsigned int)&clk->gate_ip_lcd0); 349 writel(CLK_GATE_IP_LCD1_VAL, (unsigned int)&clk->gate_ip_lcd1); 350 writel(CLK_GATE_IP_FSYS_VAL, (unsigned int)&clk->gate_ip_fsys); 351 writel(CLK_GATE_IP_GPS_VAL, (unsigned int)&clk->gate_ip_gps); 352 writel(CLK_GATE_IP_PERIL_VAL, (unsigned int)&clk->gate_ip_peril); 353 writel(CLK_GATE_IP_PERIR_VAL, (unsigned int)&clk->gate_ip_perir); 354 writel(CLK_GATE_BLOCK_VAL, (unsigned int)&clk->gate_block); 355 } 356 357 static void board_power_init(void) 358 { 359 struct exynos4_power *pwr = 360 (struct exynos4_power *)samsung_get_base_power(); 361 362 /* PS HOLD */ 363 writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control); 364 365 /* Set power down */ 366 writel(0, (unsigned int)&pwr->cam_configuration); 367 writel(0, (unsigned int)&pwr->tv_configuration); 368 writel(0, (unsigned int)&pwr->mfc_configuration); 369 writel(0, (unsigned int)&pwr->g3d_configuration); 370 writel(0, (unsigned int)&pwr->lcd1_configuration); 371 writel(0, (unsigned int)&pwr->gps_configuration); 372 writel(0, (unsigned int)&pwr->gps_alive_configuration); 373 374 /* It is necessary to power down core 1 */ 375 /* to successfully boot CPU1 in kernel */ 376 writel(0, (unsigned int)&pwr->arm_core1_configuration); 377 } 378 379 static void exynos_uart_init(void) 380 { 381 /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ 382 gpio_request(EXYNOS4_GPIO_Y47, "uart_sel"); 383 gpio_set_pull(EXYNOS4_GPIO_Y47, S5P_GPIO_PULL_UP); 384 gpio_direction_output(EXYNOS4_GPIO_Y47, 1); 385 } 386 387 int exynos_early_init_f(void) 388 { 389 wdt_stop(); 390 pmic_reset(); 391 board_clock_init(); 392 exynos_uart_init(); 393 board_power_init(); 394 395 return 0; 396 } 397 398 void exynos_reset_lcd(void) 399 { 400 gpio_request(EXYNOS4_GPIO_Y45, "lcd_reset"); 401 gpio_direction_output(EXYNOS4_GPIO_Y45, 1); 402 udelay(10000); 403 gpio_direction_output(EXYNOS4_GPIO_Y45, 0); 404 udelay(10000); 405 gpio_direction_output(EXYNOS4_GPIO_Y45, 1); 406 } 407 408 int lcd_power(void) 409 { 410 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 411 int ret = 0; 412 struct pmic *p = pmic_get("MAX8997_PMIC"); 413 if (!p) 414 return -ENODEV; 415 416 if (pmic_probe(p)) 417 return 0; 418 419 /* LDO15 voltage: 2.2v */ 420 ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); 421 /* LDO13 voltage: 3.0v */ 422 ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); 423 424 if (ret) { 425 puts("MAX8997 LDO setting error!\n"); 426 return -1; 427 } 428 #endif 429 return 0; 430 } 431 432 int mipi_power(void) 433 { 434 #ifndef CONFIG_DM_I2C /* TODO(maintainer): Convert to driver model */ 435 int ret = 0; 436 struct pmic *p = pmic_get("MAX8997_PMIC"); 437 if (!p) 438 return -ENODEV; 439 440 if (pmic_probe(p)) 441 return 0; 442 443 /* LDO3 voltage: 1.1v */ 444 ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); 445 /* LDO4 voltage: 1.8v */ 446 ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); 447 448 if (ret) { 449 puts("MAX8997 LDO setting error!\n"); 450 return -1; 451 } 452 #endif 453 return 0; 454 } 455 456 #ifdef CONFIG_LCD 457 void exynos_lcd_misc_init(vidinfo_t *vid) 458 { 459 #ifdef CONFIG_TIZEN 460 get_tizen_logo_info(vid); 461 #endif 462 #ifdef CONFIG_S6E8AX0 463 s6e8ax0_init(); 464 setenv("lcdinfo", "lcd=s6e8ax0"); 465 #endif 466 } 467 #endif 468