1 /* 2 * (C) Copyright 2013 SAMSUNG Electronics 3 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cros_ec.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <spi.h> 13 #include <tmu.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/arch/board.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/dwmmc.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/power.h> 23 #include <power/pmic.h> 24 #include <asm/arch/sromc.h> 25 #include <power/max77686_pmic.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 struct local_info { 30 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ 31 int cros_ec_err; /* Error for cros_ec, 0 if ok */ 32 }; 33 34 static struct local_info local; 35 36 int __exynos_early_init_f(void) 37 { 38 return 0; 39 } 40 int exynos_early_init_f(void) 41 __attribute__((weak, alias("__exynos_early_init_f"))); 42 43 int __exynos_power_init(void) 44 { 45 return 0; 46 } 47 int exynos_power_init(void) 48 __attribute__((weak, alias("__exynos_power_init"))); 49 50 #if defined CONFIG_EXYNOS_TMU 51 /* Boot Time Thermal Analysis for SoC temperature threshold breach */ 52 static void boot_temp_check(void) 53 { 54 int temp; 55 56 switch (tmu_monitor(&temp)) { 57 case TMU_STATUS_NORMAL: 58 break; 59 case TMU_STATUS_TRIPPED: 60 /* 61 * Status TRIPPED ans WARNING means corresponding threshold 62 * breach 63 */ 64 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); 65 set_ps_hold_ctrl(); 66 hang(); 67 break; 68 case TMU_STATUS_WARNING: 69 puts("EXYNOS_TMU: WARNING! Temperature very high\n"); 70 break; 71 case TMU_STATUS_INIT: 72 /* 73 * TMU_STATUS_INIT means something is wrong with temperature 74 * sensing and TMU status was changed back from NORMAL to INIT. 75 */ 76 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); 77 break; 78 default: 79 debug("EXYNOS_TMU: Unknown TMU state\n"); 80 } 81 } 82 #endif 83 84 int board_init(void) 85 { 86 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 87 #if defined CONFIG_EXYNOS_TMU 88 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { 89 debug("%s: Failed to init TMU\n", __func__); 90 return -1; 91 } 92 boot_temp_check(); 93 #endif 94 95 #ifdef CONFIG_EXYNOS_SPI 96 spi_init(); 97 #endif 98 return exynos_init(); 99 } 100 101 int dram_init(void) 102 { 103 int i; 104 u32 addr; 105 106 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 107 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 108 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); 109 } 110 return 0; 111 } 112 113 void dram_init_banksize(void) 114 { 115 int i; 116 u32 addr, size; 117 118 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 119 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 120 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); 121 122 gd->bd->bi_dram[i].start = addr; 123 gd->bd->bi_dram[i].size = size; 124 } 125 } 126 127 static int board_uart_init(void) 128 { 129 int err, uart_id, ret = 0; 130 131 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { 132 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); 133 if (err) { 134 debug("UART%d not configured\n", 135 (uart_id - PERIPH_ID_UART0)); 136 ret |= err; 137 } 138 } 139 return ret; 140 } 141 142 #ifdef CONFIG_BOARD_EARLY_INIT_F 143 int board_early_init_f(void) 144 { 145 int err; 146 147 err = board_uart_init(); 148 if (err) { 149 debug("UART init failed\n"); 150 return err; 151 } 152 153 #ifdef CONFIG_SYS_I2C_INIT_BOARD 154 board_i2c_init(gd->fdt_blob); 155 #endif 156 157 return exynos_early_init_f(); 158 } 159 #endif 160 161 struct cros_ec_dev *board_get_cros_ec_dev(void) 162 { 163 return local.cros_ec_dev; 164 } 165 166 #ifdef CONFIG_CROS_EC 167 static int board_init_cros_ec_devices(const void *blob) 168 { 169 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); 170 if (local.cros_ec_err) 171 return -1; /* Will report in board_late_init() */ 172 173 return 0; 174 } 175 #endif 176 177 #if defined(CONFIG_POWER) 178 #ifdef CONFIG_POWER_MAX77686 179 static int pmic_reg_update(struct pmic *p, int reg, uint regval) 180 { 181 u32 val; 182 int ret = 0; 183 184 ret = pmic_reg_read(p, reg, &val); 185 if (ret) { 186 debug("%s: PMIC %d register read failed\n", __func__, reg); 187 return -1; 188 } 189 val |= regval; 190 ret = pmic_reg_write(p, reg, val); 191 if (ret) { 192 debug("%s: PMIC %d register write failed\n", __func__, reg); 193 return -1; 194 } 195 return 0; 196 } 197 198 static int max77686_init(void) 199 { 200 struct pmic *p; 201 202 if (pmic_init(I2C_PMIC)) 203 return -1; 204 205 p = pmic_get("MAX77686_PMIC"); 206 if (!p) 207 return -ENODEV; 208 209 if (pmic_probe(p)) 210 return -1; 211 212 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) 213 return -1; 214 215 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, 216 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) 217 return -1; 218 219 /* VDD_MIF */ 220 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, 221 MAX77686_BUCK1OUT_1V)) { 222 debug("%s: PMIC %d register write failed\n", __func__, 223 MAX77686_REG_PMIC_BUCK1OUT); 224 return -1; 225 } 226 227 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, 228 MAX77686_BUCK1CTRL_EN)) 229 return -1; 230 231 /* VDD_ARM */ 232 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, 233 MAX77686_BUCK2DVS1_1_3V)) { 234 debug("%s: PMIC %d register write failed\n", __func__, 235 MAX77686_REG_PMIC_BUCK2DVS1); 236 return -1; 237 } 238 239 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, 240 MAX77686_BUCK2CTRL_ON)) 241 return -1; 242 243 /* VDD_INT */ 244 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, 245 MAX77686_BUCK3DVS1_1_0125V)) { 246 debug("%s: PMIC %d register write failed\n", __func__, 247 MAX77686_REG_PMIC_BUCK3DVS1); 248 return -1; 249 } 250 251 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, 252 MAX77686_BUCK3CTRL_ON)) 253 return -1; 254 255 /* VDD_G3D */ 256 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, 257 MAX77686_BUCK4DVS1_1_2V)) { 258 debug("%s: PMIC %d register write failed\n", __func__, 259 MAX77686_REG_PMIC_BUCK4DVS1); 260 return -1; 261 } 262 263 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, 264 MAX77686_BUCK3CTRL_ON)) 265 return -1; 266 267 /* VDD_LDO2 */ 268 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, 269 MAX77686_LD02CTRL1_1_5V | EN_LDO)) 270 return -1; 271 272 /* VDD_LDO3 */ 273 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, 274 MAX77686_LD03CTRL1_1_8V | EN_LDO)) 275 return -1; 276 277 /* VDD_LDO5 */ 278 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, 279 MAX77686_LD05CTRL1_1_8V | EN_LDO)) 280 return -1; 281 282 /* VDD_LDO10 */ 283 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, 284 MAX77686_LD10CTRL1_1_8V | EN_LDO)) 285 return -1; 286 287 return 0; 288 } 289 #endif 290 291 int power_init_board(void) 292 { 293 int ret = 0; 294 295 set_ps_hold_ctrl(); 296 297 #ifdef CONFIG_POWER_MAX77686 298 ret = max77686_init(); 299 #endif 300 301 return exynos_power_init(); 302 } 303 #endif 304 305 #ifdef CONFIG_OF_CONTROL 306 static int decode_sromc(const void *blob, struct fdt_sromc *config) 307 { 308 int err; 309 int node; 310 311 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); 312 if (node < 0) { 313 debug("Could not find SROMC node\n"); 314 return node; 315 } 316 317 config->bank = fdtdec_get_int(blob, node, "bank", 0); 318 config->width = fdtdec_get_int(blob, node, "width", 2); 319 320 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, 321 FDT_SROM_TIMING_COUNT); 322 if (err < 0) { 323 debug("Could not decode SROMC configuration Error: %s\n", 324 fdt_strerror(err)); 325 return -FDT_ERR_NOTFOUND; 326 } 327 return 0; 328 } 329 330 int board_eth_init(bd_t *bis) 331 { 332 #ifdef CONFIG_SMC911X 333 u32 smc_bw_conf, smc_bc_conf; 334 struct fdt_sromc config; 335 fdt_addr_t base_addr; 336 int node; 337 338 node = decode_sromc(gd->fdt_blob, &config); 339 if (node < 0) { 340 debug("%s: Could not find sromc configuration\n", __func__); 341 return 0; 342 } 343 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); 344 if (node < 0) { 345 debug("%s: Could not find lan9215 configuration\n", __func__); 346 return 0; 347 } 348 349 /* We now have a node, so any problems from now on are errors */ 350 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); 351 if (base_addr == FDT_ADDR_T_NONE) { 352 debug("%s: Could not find lan9215 address\n", __func__); 353 return -1; 354 } 355 356 /* Ethernet needs data bus width of 16 bits */ 357 if (config.width != 2) { 358 debug("%s: Unsupported bus width %d\n", __func__, 359 config.width); 360 return -1; 361 } 362 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) 363 | SROMC_BYTE_ENABLE(config.bank); 364 365 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | 366 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | 367 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | 368 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | 369 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | 370 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | 371 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); 372 373 /* Select and configure the SROMC bank */ 374 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); 375 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); 376 return smc911x_initialize(0, base_addr); 377 #endif 378 return 0; 379 } 380 381 #ifdef CONFIG_GENERIC_MMC 382 int board_mmc_init(bd_t *bis) 383 { 384 int ret; 385 386 /* dwmmc initializattion for available channels */ 387 ret = exynos_dwmmc_init(gd->fdt_blob); 388 if (ret) 389 debug("dwmmc init failed\n"); 390 391 return ret; 392 } 393 #endif 394 395 #ifdef CONFIG_DISPLAY_BOARDINFO 396 int checkboard(void) 397 { 398 const char *board_name; 399 400 board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); 401 printf("Board: %s\n", board_name ? board_name : "unknown"); 402 403 return 0; 404 } 405 #endif 406 #endif /* CONFIG_OF_CONTROL */ 407 408 #ifdef CONFIG_BOARD_LATE_INIT 409 int board_late_init(void) 410 { 411 stdio_print_current_devices(); 412 413 if (local.cros_ec_err) { 414 /* Force console on */ 415 gd->flags &= ~GD_FLG_SILENT; 416 417 printf("cros-ec communications failure %d\n", 418 local.cros_ec_err); 419 puts("\nPlease reset with Power+Refresh\n\n"); 420 panic("Cannot init cros-ec device"); 421 return -1; 422 } 423 return 0; 424 } 425 #endif 426 427 int arch_early_init_r(void) 428 { 429 #ifdef CONFIG_CROS_EC 430 if (board_init_cros_ec_devices(gd->fdt_blob)) { 431 printf("%s: Failed to init EC\n", __func__); 432 return 0; 433 } 434 #endif 435 436 return 0; 437 } 438