1 /* 2 * (C) Copyright 2013 SAMSUNG Electronics 3 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <cros_ec.h> 10 #include <errno.h> 11 #include <fdtdec.h> 12 #include <spi.h> 13 #include <tmu.h> 14 #include <netdev.h> 15 #include <asm/io.h> 16 #include <asm/arch/board.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/dwmmc.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/mmc.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch/power.h> 23 #include <power/pmic.h> 24 #include <asm/arch/sromc.h> 25 #include <power/max77686_pmic.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 struct local_info { 30 struct cros_ec_dev *cros_ec_dev; /* Pointer to cros_ec device */ 31 int cros_ec_err; /* Error for cros_ec, 0 if ok */ 32 }; 33 34 static struct local_info local; 35 36 #if defined CONFIG_EXYNOS_TMU 37 /* Boot Time Thermal Analysis for SoC temperature threshold breach */ 38 static void boot_temp_check(void) 39 { 40 int temp; 41 42 switch (tmu_monitor(&temp)) { 43 case TMU_STATUS_NORMAL: 44 break; 45 case TMU_STATUS_TRIPPED: 46 /* 47 * Status TRIPPED ans WARNING means corresponding threshold 48 * breach 49 */ 50 puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); 51 set_ps_hold_ctrl(); 52 hang(); 53 break; 54 case TMU_STATUS_WARNING: 55 puts("EXYNOS_TMU: WARNING! Temperature very high\n"); 56 break; 57 case TMU_STATUS_INIT: 58 /* 59 * TMU_STATUS_INIT means something is wrong with temperature 60 * sensing and TMU status was changed back from NORMAL to INIT. 61 */ 62 puts("EXYNOS_TMU: WARNING! Temperature sensing not done\n"); 63 break; 64 default: 65 debug("EXYNOS_TMU: Unknown TMU state\n"); 66 } 67 } 68 #endif 69 70 int board_init(void) 71 { 72 gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); 73 #if defined CONFIG_EXYNOS_TMU 74 if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { 75 debug("%s: Failed to init TMU\n", __func__); 76 return -1; 77 } 78 boot_temp_check(); 79 #endif 80 81 #ifdef CONFIG_EXYNOS_SPI 82 spi_init(); 83 #endif 84 return exynos_init(); 85 } 86 87 int dram_init(void) 88 { 89 int i; 90 u32 addr; 91 92 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 93 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 94 gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE); 95 } 96 return 0; 97 } 98 99 void dram_init_banksize(void) 100 { 101 int i; 102 u32 addr, size; 103 104 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 105 addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE); 106 size = get_ram_size((long *)addr, SDRAM_BANK_SIZE); 107 108 gd->bd->bi_dram[i].start = addr; 109 gd->bd->bi_dram[i].size = size; 110 } 111 } 112 113 static int board_uart_init(void) 114 { 115 int err, uart_id, ret = 0; 116 117 for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) { 118 err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE); 119 if (err) { 120 debug("UART%d not configured\n", 121 (uart_id - PERIPH_ID_UART0)); 122 ret |= err; 123 } 124 } 125 return ret; 126 } 127 128 #ifdef CONFIG_BOARD_EARLY_INIT_F 129 int board_early_init_f(void) 130 { 131 int err; 132 133 err = board_uart_init(); 134 if (err) { 135 debug("UART init failed\n"); 136 return err; 137 } 138 139 #ifdef CONFIG_SYS_I2C_INIT_BOARD 140 board_i2c_init(gd->fdt_blob); 141 #endif 142 143 return err; 144 } 145 #endif 146 147 struct cros_ec_dev *board_get_cros_ec_dev(void) 148 { 149 return local.cros_ec_dev; 150 } 151 152 static int board_init_cros_ec_devices(const void *blob) 153 { 154 local.cros_ec_err = cros_ec_init(blob, &local.cros_ec_dev); 155 if (local.cros_ec_err) 156 return -1; /* Will report in board_late_init() */ 157 158 return 0; 159 } 160 161 #if defined(CONFIG_POWER) 162 #ifdef CONFIG_POWER_MAX77686 163 static int pmic_reg_update(struct pmic *p, int reg, uint regval) 164 { 165 u32 val; 166 int ret = 0; 167 168 ret = pmic_reg_read(p, reg, &val); 169 if (ret) { 170 debug("%s: PMIC %d register read failed\n", __func__, reg); 171 return -1; 172 } 173 val |= regval; 174 ret = pmic_reg_write(p, reg, val); 175 if (ret) { 176 debug("%s: PMIC %d register write failed\n", __func__, reg); 177 return -1; 178 } 179 return 0; 180 } 181 182 static int max77686_init(void) 183 { 184 struct pmic *p; 185 186 if (pmic_init(I2C_PMIC)) 187 return -1; 188 189 p = pmic_get("MAX77686_PMIC"); 190 if (!p) 191 return -ENODEV; 192 193 if (pmic_probe(p)) 194 return -1; 195 196 if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) 197 return -1; 198 199 if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, 200 MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) 201 return -1; 202 203 /* VDD_MIF */ 204 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, 205 MAX77686_BUCK1OUT_1V)) { 206 debug("%s: PMIC %d register write failed\n", __func__, 207 MAX77686_REG_PMIC_BUCK1OUT); 208 return -1; 209 } 210 211 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, 212 MAX77686_BUCK1CTRL_EN)) 213 return -1; 214 215 /* VDD_ARM */ 216 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, 217 MAX77686_BUCK2DVS1_1_3V)) { 218 debug("%s: PMIC %d register write failed\n", __func__, 219 MAX77686_REG_PMIC_BUCK2DVS1); 220 return -1; 221 } 222 223 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, 224 MAX77686_BUCK2CTRL_ON)) 225 return -1; 226 227 /* VDD_INT */ 228 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, 229 MAX77686_BUCK3DVS1_1_0125V)) { 230 debug("%s: PMIC %d register write failed\n", __func__, 231 MAX77686_REG_PMIC_BUCK3DVS1); 232 return -1; 233 } 234 235 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, 236 MAX77686_BUCK3CTRL_ON)) 237 return -1; 238 239 /* VDD_G3D */ 240 if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, 241 MAX77686_BUCK4DVS1_1_2V)) { 242 debug("%s: PMIC %d register write failed\n", __func__, 243 MAX77686_REG_PMIC_BUCK4DVS1); 244 return -1; 245 } 246 247 if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, 248 MAX77686_BUCK3CTRL_ON)) 249 return -1; 250 251 /* VDD_LDO2 */ 252 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, 253 MAX77686_LD02CTRL1_1_5V | EN_LDO)) 254 return -1; 255 256 /* VDD_LDO3 */ 257 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, 258 MAX77686_LD03CTRL1_1_8V | EN_LDO)) 259 return -1; 260 261 /* VDD_LDO5 */ 262 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, 263 MAX77686_LD05CTRL1_1_8V | EN_LDO)) 264 return -1; 265 266 /* VDD_LDO10 */ 267 if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, 268 MAX77686_LD10CTRL1_1_8V | EN_LDO)) 269 return -1; 270 271 return 0; 272 } 273 #endif 274 275 int power_init_board(void) 276 { 277 int ret = 0; 278 279 set_ps_hold_ctrl(); 280 281 #ifdef CONFIG_POWER_MAX77686 282 ret = max77686_init(); 283 #endif 284 285 return ret; 286 } 287 #endif 288 289 #ifdef CONFIG_OF_CONTROL 290 static int decode_sromc(const void *blob, struct fdt_sromc *config) 291 { 292 int err; 293 int node; 294 295 node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_SROMC); 296 if (node < 0) { 297 debug("Could not find SROMC node\n"); 298 return node; 299 } 300 301 config->bank = fdtdec_get_int(blob, node, "bank", 0); 302 config->width = fdtdec_get_int(blob, node, "width", 2); 303 304 err = fdtdec_get_int_array(blob, node, "srom-timing", config->timing, 305 FDT_SROM_TIMING_COUNT); 306 if (err < 0) { 307 debug("Could not decode SROMC configuration Error: %s\n", 308 fdt_strerror(err)); 309 return -FDT_ERR_NOTFOUND; 310 } 311 return 0; 312 } 313 314 int board_eth_init(bd_t *bis) 315 { 316 #ifdef CONFIG_SMC911X 317 u32 smc_bw_conf, smc_bc_conf; 318 struct fdt_sromc config; 319 fdt_addr_t base_addr; 320 int node; 321 322 node = decode_sromc(gd->fdt_blob, &config); 323 if (node < 0) { 324 debug("%s: Could not find sromc configuration\n", __func__); 325 return 0; 326 } 327 node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215); 328 if (node < 0) { 329 debug("%s: Could not find lan9215 configuration\n", __func__); 330 return 0; 331 } 332 333 /* We now have a node, so any problems from now on are errors */ 334 base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg"); 335 if (base_addr == FDT_ADDR_T_NONE) { 336 debug("%s: Could not find lan9215 address\n", __func__); 337 return -1; 338 } 339 340 /* Ethernet needs data bus width of 16 bits */ 341 if (config.width != 2) { 342 debug("%s: Unsupported bus width %d\n", __func__, 343 config.width); 344 return -1; 345 } 346 smc_bw_conf = SROMC_DATA16_WIDTH(config.bank) 347 | SROMC_BYTE_ENABLE(config.bank); 348 349 smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) | 350 SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) | 351 SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) | 352 SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) | 353 SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) | 354 SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) | 355 SROMC_BC_PMC(config.timing[FDT_SROM_PMC]); 356 357 /* Select and configure the SROMC bank */ 358 exynos_pinmux_config(PERIPH_ID_SROMC, config.bank); 359 s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf); 360 return smc911x_initialize(0, base_addr); 361 #endif 362 return 0; 363 } 364 365 #ifdef CONFIG_GENERIC_MMC 366 int board_mmc_init(bd_t *bis) 367 { 368 int ret; 369 370 /* dwmmc initializattion for available channels */ 371 ret = exynos_dwmmc_init(gd->fdt_blob); 372 if (ret) 373 debug("dwmmc init failed\n"); 374 375 return ret; 376 } 377 #endif 378 #endif 379 380 #ifdef CONFIG_BOARD_LATE_INIT 381 int board_late_init(void) 382 { 383 stdio_print_current_devices(); 384 385 if (local.cros_ec_err) { 386 /* Force console on */ 387 gd->flags &= ~GD_FLG_SILENT; 388 389 printf("cros-ec communications failure %d\n", 390 local.cros_ec_err); 391 puts("\nPlease reset with Power+Refresh\n\n"); 392 panic("Cannot init cros-ec device"); 393 return -1; 394 } 395 return 0; 396 } 397 #endif 398 399 int arch_early_init_r(void) 400 { 401 #ifdef CONFIG_CROS_EC 402 if (board_init_cros_ec_devices(gd->fdt_blob)) { 403 printf("%s: Failed to init EC\n", __func__); 404 return 0; 405 } 406 #endif 407 408 return 0; 409 } 410