1b9dcc643SXuhui Lin /*
2b9dcc643SXuhui Lin * SPDX-License-Identifier: GPL-2.0+
3b9dcc643SXuhui Lin *
4b9dcc643SXuhui Lin * (C) Copyright 2024 Rockchip Electronics Co., Ltd
5b9dcc643SXuhui Lin */
6b9dcc643SXuhui Lin
7b9dcc643SXuhui Lin #include <common.h>
8b9dcc643SXuhui Lin #include <asm/io.h>
9b9dcc643SXuhui Lin #include <dwc3-uboot.h>
10b9dcc643SXuhui Lin #include <usb.h>
11b9dcc643SXuhui Lin
12b9dcc643SXuhui Lin DECLARE_GLOBAL_DATA_PTR;
13b9dcc643SXuhui Lin
14*1d8f0870SWilliam Wu #define PERI_CRU_BASE 0x20000000
15*1d8f0870SWilliam Wu #define PERICRU_PERISOFTRST_CON06 0x0a18
16*1d8f0870SWilliam Wu #define GRF_SYS_BASE 0x20150000
17*1d8f0870SWilliam Wu #define GRF_SYS_USBPHY_CON0 0x0050
18*1d8f0870SWilliam Wu #define GRF_SYS_USBPHY_CON2 0x0058
19*1d8f0870SWilliam Wu
20b9dcc643SXuhui Lin #ifdef CONFIG_USB_DWC3
21b9dcc643SXuhui Lin static struct dwc3_device dwc3_device_data = {
22b9dcc643SXuhui Lin .maximum_speed = USB_SPEED_HIGH,
23b9dcc643SXuhui Lin .base = 0x20b00000,
24b9dcc643SXuhui Lin .dr_mode = USB_DR_MODE_PERIPHERAL,
25b9dcc643SXuhui Lin .index = 0,
26b9dcc643SXuhui Lin .dis_u2_susphy_quirk = 1,
27b9dcc643SXuhui Lin .usb2_phyif_utmi_width = 16,
28b9dcc643SXuhui Lin };
29b9dcc643SXuhui Lin
usb_gadget_handle_interrupts(void)30b9dcc643SXuhui Lin int usb_gadget_handle_interrupts(void)
31b9dcc643SXuhui Lin {
32b9dcc643SXuhui Lin dwc3_uboot_handle_interrupt(0);
33b9dcc643SXuhui Lin return 0;
34b9dcc643SXuhui Lin }
35b9dcc643SXuhui Lin
usb_reset_otg_controller(void)36*1d8f0870SWilliam Wu static void usb_reset_otg_controller(void)
37*1d8f0870SWilliam Wu {
38*1d8f0870SWilliam Wu writel(0x02000200, PERI_CRU_BASE + PERICRU_PERISOFTRST_CON06);
39*1d8f0870SWilliam Wu mdelay(1);
40*1d8f0870SWilliam Wu writel(0x02000000, PERI_CRU_BASE + PERICRU_PERISOFTRST_CON06);
41*1d8f0870SWilliam Wu mdelay(1);
42*1d8f0870SWilliam Wu }
43*1d8f0870SWilliam Wu
board_usb_init(int index,enum usb_init_type init)44b9dcc643SXuhui Lin int board_usb_init(int index, enum usb_init_type init)
45b9dcc643SXuhui Lin {
46*1d8f0870SWilliam Wu usb_reset_otg_controller();
47*1d8f0870SWilliam Wu
48*1d8f0870SWilliam Wu /* Resume usb2 phy to normal mode */
49*1d8f0870SWilliam Wu writel(0x01ff0000, GRF_SYS_BASE + GRF_SYS_USBPHY_CON0);
50*1d8f0870SWilliam Wu
51*1d8f0870SWilliam Wu /* Select usb utmi bvalid from grf and set bvalid high */
52*1d8f0870SWilliam Wu writel(0xc000c000, GRF_SYS_BASE + GRF_SYS_USBPHY_CON2);
53*1d8f0870SWilliam Wu
54b9dcc643SXuhui Lin return dwc3_uboot_init(&dwc3_device_data);
55b9dcc643SXuhui Lin }
56b9dcc643SXuhui Lin #endif
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