1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * 4 * (C) Copyright 2023 Rockchip Electronics Co., Ltd 5 */ 6 7 #include <common.h> 8 #include <dwc3-uboot.h> 9 #include <usb.h> 10 #include <linux/usb/phy-rockchip-usbdp.h> 11 #include <asm/io.h> 12 #include <rockusb.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #ifdef CONFIG_USB_DWC3 17 #define CRU_BASE 0x27200000 18 #define CRU_SOFTRST_CON47 0x0abc 19 #define U3PHY_BASE 0x2b010000 20 21 static struct dwc3_device dwc3_device_data = { 22 .maximum_speed = USB_SPEED_SUPER, 23 .base = 0x23000000, 24 .dr_mode = USB_DR_MODE_PERIPHERAL, 25 .index = 0, 26 .dis_u2_susphy_quirk = 1, 27 .dis_u1u2_quirk = 1, 28 .usb2_phyif_utmi_width = 16, 29 }; 30 31 int usb_gadget_handle_interrupts(int index) 32 { 33 dwc3_uboot_handle_interrupt(0); 34 return 0; 35 } 36 37 bool rkusb_usb3_capable(void) 38 { 39 return true; 40 } 41 42 static void usb_reset_otg_controller(void) 43 { 44 writel(0x00200020, CRU_BASE + CRU_SOFTRST_CON47); 45 mdelay(1); 46 writel(0x00200000, CRU_BASE + CRU_SOFTRST_CON47); 47 mdelay(1); 48 } 49 50 int board_usb_init(int index, enum usb_init_type init) 51 { 52 u32 ret = 0; 53 54 usb_reset_otg_controller(); 55 56 #if defined(CONFIG_SUPPORT_USBPLUG) 57 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 58 59 if (rkusb_switch_usb3_enabled()) { 60 dwc3_device_data.maximum_speed = USB_SPEED_SUPER; 61 ret = rockchip_u3phy_uboot_init(U3PHY_BASE); 62 if (ret) { 63 rkusb_force_to_usb2(true); 64 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 65 } 66 } 67 #else 68 ret = rockchip_u3phy_uboot_init(U3PHY_BASE); 69 if (ret) { 70 rkusb_force_to_usb2(true); 71 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 72 } 73 #endif 74 75 return dwc3_uboot_init(&dwc3_device_data); 76 } 77 78 #if defined(CONFIG_SUPPORT_USBPLUG) 79 int board_usb_cleanup(int index, enum usb_init_type init) 80 { 81 dwc3_uboot_exit(index); 82 return 0; 83 } 84 #endif 85 86 #endif 87