1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * 4 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 5 */ 6 7 #include <common.h> 8 #include <dwc3-uboot.h> 9 #include <usb.h> 10 #include <linux/usb/phy-rockchip-naneng-combphy.h> 11 #include <asm/io.h> 12 #include <asm/arch-rockchip/cpu.h> 13 #include <rockusb.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 #ifdef CONFIG_USB_DWC3 18 #define CRU_BASE 0xfdd20000 19 #define CRU_SOFTRST_CON09 0x0424 20 21 static struct dwc3_device dwc3_device_data = { 22 .maximum_speed = USB_SPEED_SUPER, 23 .base = 0xfcc00000, 24 .dr_mode = USB_DR_MODE_PERIPHERAL, 25 .index = 0, 26 .dis_u2_susphy_quirk = 1, 27 .dis_u1u2_quirk = 1, 28 .usb2_phyif_utmi_width = 16, 29 }; 30 31 int usb_gadget_handle_interrupts(int index) 32 { 33 dwc3_uboot_handle_interrupt(0); 34 return 0; 35 } 36 37 bool rkusb_usb3_capable(void) 38 { 39 return true; 40 } 41 42 static void usb_reset_otg_controller(void) 43 { 44 writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON09); 45 mdelay(1); 46 writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON09); 47 mdelay(1); 48 } 49 50 int board_usb_init(int index, enum usb_init_type init) 51 { 52 u32 ret = 0; 53 54 usb_reset_otg_controller(); 55 56 #if defined(CONFIG_SUPPORT_USBPLUG) 57 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 58 59 if (rkusb_switch_usb3_enabled()) { 60 dwc3_device_data.maximum_speed = USB_SPEED_SUPER; 61 ret = rockchip_combphy_usb3_uboot_init(); 62 if (ret) { 63 rkusb_force_to_usb2(true); 64 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 65 } 66 } 67 #else 68 if (soc_is_rk3566()) { 69 rkusb_force_to_usb2(true); 70 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 71 } else { 72 ret = rockchip_combphy_usb3_uboot_init(); 73 if (ret) { 74 rkusb_force_to_usb2(true); 75 dwc3_device_data.maximum_speed = USB_SPEED_HIGH; 76 } 77 } 78 #endif 79 return dwc3_uboot_init(&dwc3_device_data); 80 } 81 82 #if defined(CONFIG_SUPPORT_USBPLUG) 83 int board_usb_cleanup(int index, enum usb_init_type init) 84 { 85 dwc3_uboot_exit(index); 86 return 0; 87 } 88 #endif 89 90 #endif 91