1 /* 2 * board/renesas/silk/silk.c 3 * 4 * Copyright (C) 2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Cogent Embedded, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <asm/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/mmc.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include <div64.h> 27 #include "qos.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define CLK2MHZ(clk) (clk / 1000 / 1000) 32 void s_init(void) 33 { 34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36 37 /* Watchdog init */ 38 writel(0xA5A5A500, &rwdt->rwtcsra); 39 writel(0xA5A5A500, &swdt->swtcsra); 40 41 /* QoS */ 42 qos_init(); 43 } 44 45 #define TMU0_MSTP125 (1 << 25) 46 #define SCIF2_MSTP719 (1 << 19) 47 #define ETHER_MSTP813 (1 << 13) 48 #define IIC1_MSTP323 (1 << 23) 49 #define MMC0_MSTP315 (1 << 15) 50 51 int board_early_init_f(void) 52 { 53 /* TMU */ 54 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 55 56 /* SCIF2 */ 57 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 58 59 /* ETHER */ 60 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 61 62 /* IIC1 / sh-i2c ch1 */ 63 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); 64 65 #ifdef CONFIG_SH_MMCIF 66 /* MMC */ 67 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); 68 #endif 69 return 0; 70 } 71 72 /* LSI pin pull-up control */ 73 #define PUPR3 0xe606010C 74 #define PUPR3_ETH 0x006FF800 75 #define PUPR1 0xe6060104 76 #define PUPR1_DREQ0_N (1 << 20) 77 int board_init(void) 78 { 79 /* adress of boot parameters */ 80 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 81 82 /* Init PFC controller */ 83 r8a7794_pinmux_init(); 84 85 /* Ether Enable */ 86 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 87 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 88 gpio_request(GPIO_FN_ETH_RXD0, NULL); 89 gpio_request(GPIO_FN_ETH_RXD1, NULL); 90 gpio_request(GPIO_FN_ETH_LINK, NULL); 91 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 92 gpio_request(GPIO_FN_ETH_MDIO, NULL); 93 gpio_request(GPIO_FN_ETH_TXD1, NULL); 94 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 95 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 96 gpio_request(GPIO_FN_ETH_TXD0, NULL); 97 gpio_request(GPIO_FN_ETH_MDC, NULL); 98 gpio_request(GPIO_FN_IRQ8, NULL); 99 100 /* PHY reset */ 101 mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); 102 gpio_request(GPIO_GP_1_24, NULL); 103 mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); 104 105 gpio_direction_output(GPIO_GP_1_24, 0); 106 mdelay(20); 107 gpio_set_value(GPIO_GP_1_24, 1); 108 udelay(1); 109 110 return 0; 111 } 112 113 #define CXR24 0xEE7003C0 /* MAC address high register */ 114 #define CXR25 0xEE7003C8 /* MAC address low register */ 115 int board_eth_init(bd_t *bis) 116 { 117 #ifdef CONFIG_SH_ETHER 118 int ret = -ENODEV; 119 u32 val; 120 unsigned char enetaddr[6]; 121 122 ret = sh_eth_initialize(bis); 123 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 124 return ret; 125 126 /* Set Mac address */ 127 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 128 enetaddr[2] << 8 | enetaddr[3]; 129 writel(val, CXR24); 130 131 val = enetaddr[4] << 8 | enetaddr[5]; 132 writel(val, CXR25); 133 134 return ret; 135 #else 136 return 0; 137 #endif 138 } 139 140 int board_mmc_init(bd_t *bis) 141 { 142 int ret = 0; 143 144 #ifdef CONFIG_SH_MMCIF 145 /* MMC0 */ 146 gpio_request(GPIO_GP_4_31, NULL); 147 gpio_direction_output(GPIO_GP_4_31, 1); 148 149 ret = mmcif_mmc_init(); 150 #endif 151 return ret; 152 } 153 154 int dram_init(void) 155 { 156 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 157 158 return 0; 159 } 160 161 const struct rmobile_sysinfo sysinfo = { 162 CONFIG_RMOBILE_BOARD_STRING 163 }; 164 165 void reset_cpu(ulong addr) 166 { 167 u8 val; 168 169 i2c_set_bus_num(1); /* PowerIC connected to ch1 */ 170 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 171 val |= 0x02; 172 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 173 } 174 175 static const struct sh_serial_platdata serial_platdata = { 176 .base = SCIF2_BASE, 177 .type = PORT_SCIF, 178 .clk = 14745600, 179 .clk_mode = EXT_CLK, 180 }; 181 182 U_BOOT_DEVICE(alt_serials) = { 183 .name = "serial_sh", 184 .platdata = &serial_platdata, 185 }; 186