1 /* 2 * board/renesas/salvator-x/salvator-x.c 3 * This file is Salvator-X board support. 4 * 5 * Copyright (C) 2015 Renesas Electronics Corporation 6 * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <malloc.h> 13 #include <netdev.h> 14 #include <dm.h> 15 #include <dm/platform_data/serial_sh.h> 16 #include <asm/processor.h> 17 #include <asm/mach-types.h> 18 #include <asm/io.h> 19 #include <linux/errno.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/gpio.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/rmobile.h> 24 #include <asm/arch/rcar-mstp.h> 25 #include <i2c.h> 26 #include <mmc.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define CPGWPCR 0xE6150904 31 #define CPGWPR 0xE615090C 32 33 #define CLK2MHZ(clk) (clk / 1000 / 1000) 34 void s_init(void) 35 { 36 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 37 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 38 39 /* Watchdog init */ 40 writel(0xA5A5A500, &rwdt->rwtcsra); 41 writel(0xA5A5A500, &swdt->swtcsra); 42 43 writel(0xA5A50000, CPGWPCR); 44 writel(0xFFFFFFFF, CPGWPR); 45 } 46 47 #define GSX_MSTP112 BIT(12) /* 3DG */ 48 #define TMU0_MSTP125 BIT(25) /* secure */ 49 #define TMU1_MSTP124 BIT(24) /* non-secure */ 50 #define SCIF2_MSTP310 BIT(10) /* SCIF2 */ 51 52 int board_early_init_f(void) 53 { 54 /* TMU0,1 */ /* which use ? */ 55 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); 56 /* SCIF2 */ 57 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); 58 59 return 0; 60 } 61 62 /* SYSC */ 63 /* R/- 32 Power status register 2(3DG) */ 64 #define SYSC_PWRSR2 0xE6180100 65 /* -/W 32 Power resume control register 2 (3DG) */ 66 #define SYSC_PWRONCR2 0xE618010C 67 68 int board_init(void) 69 { 70 /* adress of boot parameters */ 71 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; 72 73 /* Init PFC controller */ 74 r8a7795_pinmux_init(); 75 76 /* GSX: force power and clock supply */ 77 writel(0x0000001F, SYSC_PWRONCR2); 78 while (readl(SYSC_PWRSR2) != 0x000003E0) 79 mdelay(20); 80 81 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); 82 83 return 0; 84 } 85 86 int dram_init(void) 87 { 88 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 89 90 return 0; 91 } 92 93 const struct rmobile_sysinfo sysinfo = { 94 CONFIG_RCAR_BOARD_STRING 95 }; 96 97 #define RST_BASE 0xE6160000 98 #define RST_CA57RESCNT (RST_BASE + 0x40) 99 #define RST_CA53RESCNT (RST_BASE + 0x44) 100 #define RST_RSTOUTCR (RST_BASE + 0x58) 101 #define RST_CODE 0xA5A5000F 102 103 void reset_cpu(ulong addr) 104 { 105 /* only CA57 ? */ 106 writel(RST_CODE, RST_CA57RESCNT); 107 } 108 109 static const struct sh_serial_platdata serial_platdata = { 110 .base = SCIF2_BASE, 111 .type = PORT_SCIF, 112 .clk = 14745600, /* 0xE10000 */ 113 .clk_mode = EXT_CLK, 114 }; 115 116 U_BOOT_DEVICE(salvator_x_scif2) = { 117 .name = "serial_sh", 118 .platdata = &serial_platdata, 119 }; 120