199744b7eSPhil Edworthy/* 299744b7eSPhil Edworthy * Copyright (C) 2012 Renesas Electronics Europe Ltd. 399744b7eSPhil Edworthy * Copyright (C) 2012 Phil Edworthy 499744b7eSPhil Edworthy * Copyright (C) 2008 Renesas Solutions Corp. 599744b7eSPhil Edworthy * Copyright (C) 2008 Nobuhiro Iwamatsu 699744b7eSPhil Edworthy * 799744b7eSPhil Edworthy * Based on board/renesas/rsk7264/lowlevel_init.S 899744b7eSPhil Edworthy * 9*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1099744b7eSPhil Edworthy */ 1199744b7eSPhil Edworthy#include <config.h> 1299744b7eSPhil Edworthy 1399744b7eSPhil Edworthy#include <asm/processor.h> 1499744b7eSPhil Edworthy#include <asm/macro.h> 1599744b7eSPhil Edworthy 1699744b7eSPhil Edworthy .global lowlevel_init 1799744b7eSPhil Edworthy 1899744b7eSPhil Edworthy .text 1999744b7eSPhil Edworthy .align 2 2099744b7eSPhil Edworthy 2199744b7eSPhil Edworthylowlevel_init: 2299744b7eSPhil Edworthy /* Flush and enable caches (data cache in write-through mode) */ 2399744b7eSPhil Edworthy write32 CCR1_A ,CCR1_D 2499744b7eSPhil Edworthy 2599744b7eSPhil Edworthy /* Disable WDT */ 2699744b7eSPhil Edworthy write16 WTCSR_A, WTCSR_D 2799744b7eSPhil Edworthy write16 WTCNT_A, WTCNT_D 2899744b7eSPhil Edworthy 2999744b7eSPhil Edworthy /* Disable Register Bank interrupts */ 3099744b7eSPhil Edworthy write16 IBNR_A, IBNR_D 3199744b7eSPhil Edworthy 3299744b7eSPhil Edworthy /* Set clocks based on 13.225MHz xtal */ 3399744b7eSPhil Edworthy write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ 3499744b7eSPhil Edworthy 3599744b7eSPhil Edworthy /* Enable all peripherals */ 3699744b7eSPhil Edworthy write8 STBCR3_A, STBCR3_D 3799744b7eSPhil Edworthy write8 STBCR4_A, STBCR4_D 3899744b7eSPhil Edworthy write8 STBCR5_A, STBCR5_D 3999744b7eSPhil Edworthy write8 STBCR6_A, STBCR6_D 4099744b7eSPhil Edworthy write8 STBCR7_A, STBCR7_D 4199744b7eSPhil Edworthy write8 STBCR8_A, STBCR8_D 4299744b7eSPhil Edworthy write8 STBCR9_A, STBCR9_D 4399744b7eSPhil Edworthy write8 STBCR10_A, STBCR10_D 4499744b7eSPhil Edworthy 4599744b7eSPhil Edworthy /* SCIF7 and IIC2 */ 4699744b7eSPhil Edworthy write16 PJCR3_A, PJCR3_D /* TXD7 */ 4799744b7eSPhil Edworthy write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ 4899744b7eSPhil Edworthy 4999744b7eSPhil Edworthy /* Configure bus (CS0) */ 5099744b7eSPhil Edworthy write16 PFCR3_A, PFCR3_D /* A24 */ 5199744b7eSPhil Edworthy write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ 5299744b7eSPhil Edworthy write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ 5399744b7eSPhil Edworthy write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 5499744b7eSPhil Edworthy write32 CS0WCR_A, CS0WCR_D 5599744b7eSPhil Edworthy write32 CS0BCR_A, CS0BCR_D 5699744b7eSPhil Edworthy 5799744b7eSPhil Edworthy /* Configure SDRAM (CS3) */ 5899744b7eSPhil Edworthy write16 PCCR2_A, PCCR2_D /* CS3# */ 5999744b7eSPhil Edworthy write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ 6099744b7eSPhil Edworthy write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 6199744b7eSPhil Edworthy write32 CS3BCR_A, CS3BCR_D 6299744b7eSPhil Edworthy write32 CS3WCR_A, CS3WCR_D 6399744b7eSPhil Edworthy write32 SDCR_A, SDCR_D 6499744b7eSPhil Edworthy write32 RTCOR_A, RTCOR_D 6599744b7eSPhil Edworthy write32 RTCSR_A, RTCSR_D 6699744b7eSPhil Edworthy 6799744b7eSPhil Edworthy /* Configure ethernet (CS1) */ 6899744b7eSPhil Edworthy write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ 6999744b7eSPhil Edworthy write16 PHCR0_A, PHCR0_D 7099744b7eSPhil Edworthy write16 PFCR2_A, PFCR2_D /* CS1# */ 7199744b7eSPhil Edworthy write32 CS1BCR_A, CS1BCR_D /* Big endian */ 7299744b7eSPhil Edworthy write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ 7399744b7eSPhil Edworthy write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ 7499744b7eSPhil Edworthy write16 PJIOR1_A, PJIOR1_D 7599744b7eSPhil Edworthy 7699744b7eSPhil Edworthy /* wait 200us */ 7799744b7eSPhil Edworthy mov.l REPEAT_D, r3 7899744b7eSPhil Edworthy mov #0, r2 7999744b7eSPhil Edworthyrepeat0: 8099744b7eSPhil Edworthy add #1, r2 8199744b7eSPhil Edworthy cmp/hs r3, r2 8299744b7eSPhil Edworthy bf repeat0 8399744b7eSPhil Edworthy nop 8499744b7eSPhil Edworthy 8599744b7eSPhil Edworthy mov.l SDRAM_MODE, r1 8699744b7eSPhil Edworthy mov #0, r0 8799744b7eSPhil Edworthy mov.l r0, @r1 8899744b7eSPhil Edworthy 8999744b7eSPhil Edworthy nop 9099744b7eSPhil Edworthy rts 9199744b7eSPhil Edworthy 9299744b7eSPhil Edworthy .align 4 9399744b7eSPhil Edworthy 9499744b7eSPhil EdworthyCCR1_A: .long CCR1 9599744b7eSPhil EdworthyCCR1_D: .long 0x0000090B 9699744b7eSPhil Edworthy 9799744b7eSPhil EdworthySTBCR3_A: .long 0xFFFE0408 9899744b7eSPhil EdworthySTBCR4_A: .long 0xFFFE040C 9999744b7eSPhil EdworthySTBCR5_A: .long 0xFFFE0410 10099744b7eSPhil EdworthySTBCR6_A: .long 0xFFFE0414 10199744b7eSPhil EdworthySTBCR7_A: .long 0xFFFE0418 10299744b7eSPhil EdworthySTBCR8_A: .long 0xFFFE041C 10399744b7eSPhil EdworthySTBCR9_A: .long 0xFFFE0440 10499744b7eSPhil EdworthySTBCR10_A: .long 0xFFFE0444 10599744b7eSPhil EdworthySTBCR3_D: .long 0x0000001A 10699744b7eSPhil EdworthySTBCR4_D: .long 0x00000000 10799744b7eSPhil EdworthySTBCR5_D: .long 0x00000000 10899744b7eSPhil EdworthySTBCR6_D: .long 0x00000000 10999744b7eSPhil EdworthySTBCR7_D: .long 0x00000012 11099744b7eSPhil EdworthySTBCR8_D: .long 0x00000009 11199744b7eSPhil EdworthySTBCR9_D: .long 0x00000000 11299744b7eSPhil EdworthySTBCR10_D: .long 0x00000010 11399744b7eSPhil Edworthy 11499744b7eSPhil EdworthyWTCSR_A: .long 0xFFFE0000 11599744b7eSPhil EdworthyWTCNT_A: .long 0xFFFE0002 11699744b7eSPhil EdworthyWTCSR_D: .word 0xA518 11799744b7eSPhil EdworthyWTCNT_D: .word 0x5A00 11899744b7eSPhil Edworthy 11999744b7eSPhil EdworthyIBNR_A: .long 0xFFFE080E 12099744b7eSPhil EdworthyIBNR_D: .word 0x0000 12199744b7eSPhil Edworthy.align 2 12299744b7eSPhil EdworthyFRQCR_A: .long 0xFFFE0010 12399744b7eSPhil EdworthyFRQCR_D: .word 0x0015 12499744b7eSPhil Edworthy.align 2 12599744b7eSPhil Edworthy 12699744b7eSPhil EdworthyPJCR3_A: .long 0xFFFE3908 12799744b7eSPhil EdworthyPJCR3_D: .word 0x5000 12899744b7eSPhil Edworthy.align 2 12999744b7eSPhil EdworthyPECR1_A: .long 0xFFFE388C 13099744b7eSPhil EdworthyPECR1_D: .word 0x2011 13199744b7eSPhil Edworthy.align 2 13299744b7eSPhil Edworthy 13399744b7eSPhil EdworthyPFCR3_A: .long 0xFFFE38A8 13499744b7eSPhil EdworthyPFCR2_A: .long 0xFFFE38AA 13599744b7eSPhil EdworthyPBCR5_A: .long 0xFFFE3824 13699744b7eSPhil EdworthyPFCR3_D: .word 0x0010 13799744b7eSPhil EdworthyPFCR2_D: .word 0x0101 13899744b7eSPhil EdworthyPBCR5_D: .word 0x0111 13999744b7eSPhil Edworthy.align 2 14099744b7eSPhil EdworthyCS0WCR_A: .long 0xFFFC0028 14199744b7eSPhil EdworthyCS0WCR_D: .long 0x00000341 14299744b7eSPhil EdworthyCS0BCR_A: .long 0xFFFC0004 14399744b7eSPhil EdworthyCS0BCR_D: .long 0x00000400 14499744b7eSPhil Edworthy 14599744b7eSPhil EdworthyPCCR2_A: .long 0xFFFE384A 14699744b7eSPhil EdworthyPCCR1_A: .long 0xFFFE384C 14799744b7eSPhil EdworthyPCCR0_A: .long 0xFFFE384E 14899744b7eSPhil EdworthyPCCR2_D: .word 0x0001 14999744b7eSPhil EdworthyPCCR1_D: .word 0x1111 15099744b7eSPhil EdworthyPCCR0_D: .word 0x1111 15199744b7eSPhil Edworthy.align 2 15299744b7eSPhil EdworthyCS3BCR_A: .long 0xFFFC0010 15399744b7eSPhil EdworthyCS3BCR_D: .long 0x00004400 15499744b7eSPhil EdworthyCS3WCR_A: .long 0xFFFC0034 15599744b7eSPhil EdworthyCS3WCR_D: .long 0x00004912 15699744b7eSPhil EdworthySDCR_A: .long 0xFFFC004C 15799744b7eSPhil EdworthySDCR_D: .long 0x00000811 15899744b7eSPhil EdworthyRTCOR_A: .long 0xFFFC0058 15999744b7eSPhil EdworthyRTCOR_D: .long 0xA55A0035 16099744b7eSPhil EdworthyRTCSR_A: .long 0xFFFC0050 16199744b7eSPhil EdworthyRTCSR_D: .long 0xA55A0010 16299744b7eSPhil Edworthy.align 2 16399744b7eSPhil EdworthySDRAM_MODE: .long 0xFFFC5460 16499744b7eSPhil EdworthyREPEAT_D: .long 0x000033F1 16599744b7eSPhil Edworthy 16699744b7eSPhil EdworthyPHCR1_A: .long 0xFFFE38EC 16799744b7eSPhil EdworthyPHCR0_A: .long 0xFFFE38EE 16899744b7eSPhil EdworthyPHCR1_D: .word 0x2222 16999744b7eSPhil EdworthyPHCR0_D: .word 0x2222 17099744b7eSPhil Edworthy.align 2 17199744b7eSPhil EdworthyCS1BCR_A: .long 0xFFFC0008 17299744b7eSPhil EdworthyCS1BCR_D: .long 0x00000400 17399744b7eSPhil EdworthyCS1WCR_A: .long 0xFFFC002C 17499744b7eSPhil EdworthyCS1WCR_D: .long 0x00000080 17599744b7eSPhil EdworthyPJDR1_A: .long 0xFFFE3914 17699744b7eSPhil EdworthyPJDR1_D: .word 0x0000 17799744b7eSPhil Edworthy.align 2 17899744b7eSPhil EdworthyPJIOR1_A: .long 0xFFFE3910 17999744b7eSPhil EdworthyPJIOR1_D: .word 0x8000 18099744b7eSPhil Edworthy.align 2 181