17fbeb642SPhil Edworthy/* 27fbeb642SPhil Edworthy * Copyright (C) 2011 Renesas Electronics Europe Ltd. 37fbeb642SPhil Edworthy * Copyright (C) 2008 Renesas Solutions Corp. 47fbeb642SPhil Edworthy * Copyright (C) 2008 Nobuhiro Iwamatsu 57fbeb642SPhil Edworthy * 67fbeb642SPhil Edworthy * Based on board/renesas/rsk7203/lowlevel_init.S 77fbeb642SPhil Edworthy * 8*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 97fbeb642SPhil Edworthy */ 107fbeb642SPhil Edworthy#include <config.h> 117fbeb642SPhil Edworthy 127fbeb642SPhil Edworthy#include <asm/processor.h> 137fbeb642SPhil Edworthy#include <asm/macro.h> 147fbeb642SPhil Edworthy 157fbeb642SPhil Edworthy .global lowlevel_init 167fbeb642SPhil Edworthy 177fbeb642SPhil Edworthy .text 187fbeb642SPhil Edworthy .align 2 197fbeb642SPhil Edworthy 207fbeb642SPhil Edworthylowlevel_init: 217fbeb642SPhil Edworthy /* Cache setting */ 227fbeb642SPhil Edworthy write32 CCR1_A ,CCR1_D 237fbeb642SPhil Edworthy 247fbeb642SPhil Edworthy /* io_set_cpg */ 257fbeb642SPhil Edworthy write8 STBCR3_A, STBCR3_D 267fbeb642SPhil Edworthy write8 STBCR4_A, STBCR4_D 277fbeb642SPhil Edworthy write8 STBCR5_A, STBCR5_D 287fbeb642SPhil Edworthy write8 STBCR6_A, STBCR6_D 297fbeb642SPhil Edworthy write8 STBCR7_A, STBCR7_D 307fbeb642SPhil Edworthy write8 STBCR8_A, STBCR8_D 317fbeb642SPhil Edworthy 327fbeb642SPhil Edworthy /* ConfigurePortPins */ 337fbeb642SPhil Edworthy 347fbeb642SPhil Edworthy /* Leaving LED1 ON for sanity test */ 357fbeb642SPhil Edworthy write16 PJCR1_A, PJCR1_D1 367fbeb642SPhil Edworthy write16 PJCR2_A, PJCR2_D 377fbeb642SPhil Edworthy write16 PJIOR0_A, PJIOR0_D1 387fbeb642SPhil Edworthy write16 PJDR0_A, PJDR0_D 397fbeb642SPhil Edworthy write16 PJPR0_A, PJPR0_D 407fbeb642SPhil Edworthy 417fbeb642SPhil Edworthy /* Configure EN_PIN & RS_PIN */ 427fbeb642SPhil Edworthy write16 PGCR2_A, PGCR2_D 437fbeb642SPhil Edworthy write16 PGIOR0_A, PGIOR0_D 447fbeb642SPhil Edworthy 457fbeb642SPhil Edworthy /* Configure the port pins connected to UART */ 467fbeb642SPhil Edworthy write16 PJCR1_A, PJCR1_D2 477fbeb642SPhil Edworthy write16 PJIOR0_A, PJIOR0_D2 487fbeb642SPhil Edworthy 497fbeb642SPhil Edworthy /* Configure Operating Frequency */ 507fbeb642SPhil Edworthy write16 WTCSR_A, WTCSR_D0 517fbeb642SPhil Edworthy write16 WTCSR_A, WTCSR_D1 527fbeb642SPhil Edworthy write16 WTCNT_A, WTCNT_D 537fbeb642SPhil Edworthy 547fbeb642SPhil Edworthy /* Control of RESBANK */ 557fbeb642SPhil Edworthy write16 IBNR_A, IBNR_D 567fbeb642SPhil Edworthy /* Enable SCIF3 module */ 577fbeb642SPhil Edworthy write16 STBCR4_A, STBCR4_D 587fbeb642SPhil Edworthy 597fbeb642SPhil Edworthy /* Set clock mode*/ 607fbeb642SPhil Edworthy write16 FRQCR_A, FRQCR_D 617fbeb642SPhil Edworthy 627fbeb642SPhil Edworthy /* Configure Bus And Memory */ 637fbeb642SPhil Edworthyinit_bsc_cs0: 647fbeb642SPhil Edworthy 657fbeb642SPhil Edworthypfc_settings: 667fbeb642SPhil Edworthy write16 PCCR2_A, PCCR2_D 677fbeb642SPhil Edworthy write16 PCCR1_A, PCCR1_D 687fbeb642SPhil Edworthy write16 PCCR0_A, PCCR0_D 697fbeb642SPhil Edworthy 707fbeb642SPhil Edworthy write16 PBCR0_A, PBCR0_D 717fbeb642SPhil Edworthy write16 PBCR1_A, PBCR1_D 727fbeb642SPhil Edworthy write16 PBCR2_A, PBCR2_D 737fbeb642SPhil Edworthy write16 PBCR3_A, PBCR3_D 747fbeb642SPhil Edworthy write16 PBCR4_A, PBCR4_D 757fbeb642SPhil Edworthy write16 PBCR5_A, PBCR5_D 767fbeb642SPhil Edworthy 777fbeb642SPhil Edworthy write16 PDCR0_A, PDCR0_D 787fbeb642SPhil Edworthy write16 PDCR1_A, PDCR1_D 797fbeb642SPhil Edworthy write16 PDCR2_A, PDCR2_D 807fbeb642SPhil Edworthy write16 PDCR3_A, PDCR3_D 817fbeb642SPhil Edworthy 827fbeb642SPhil Edworthy write32 CS0WCR_A, CS0WCR_D 837fbeb642SPhil Edworthy write32 CS0BCR_A, CS0BCR_D 847fbeb642SPhil Edworthy 857fbeb642SPhil Edworthyinit_bsc_cs2: 867fbeb642SPhil Edworthy write16 PJCR0_A, PJCR0_D 877fbeb642SPhil Edworthy write32 CS2WCR_A, CS2WCR_D 887fbeb642SPhil Edworthy 897fbeb642SPhil Edworthyinit_sdram: 907fbeb642SPhil Edworthy write32 CS3BCR_A, CS3BCR_D 917fbeb642SPhil Edworthy write32 CS3WCR_A, CS3WCR_D 927fbeb642SPhil Edworthy write32 SDCR_A, SDCR_D 937fbeb642SPhil Edworthy write32 RTCOR_A, RTCOR_D 947fbeb642SPhil Edworthy write32 RTCSR_A, RTCSR_D 957fbeb642SPhil Edworthy 967fbeb642SPhil Edworthy /* wait 200us */ 977fbeb642SPhil Edworthy mov.l REPEAT_D, r3 987fbeb642SPhil Edworthy mov #0, r2 997fbeb642SPhil Edworthyrepeat0: 1007fbeb642SPhil Edworthy add #1, r2 1017fbeb642SPhil Edworthy cmp/hs r3, r2 1027fbeb642SPhil Edworthy bf repeat0 1037fbeb642SPhil Edworthy nop 1047fbeb642SPhil Edworthy 1057fbeb642SPhil Edworthy mov.l SDRAM_MODE, r1 1067fbeb642SPhil Edworthy mov #0, r0 1077fbeb642SPhil Edworthy mov.l r0, @r1 1087fbeb642SPhil Edworthy 1097fbeb642SPhil Edworthy nop 1107fbeb642SPhil Edworthy rts 1117fbeb642SPhil Edworthy 1127fbeb642SPhil Edworthy .align 4 1137fbeb642SPhil Edworthy 1147fbeb642SPhil EdworthyCCR1_A: .long CCR1 1157fbeb642SPhil EdworthyCCR1_D: .long 0x0000090B 1167fbeb642SPhil EdworthyFRQCR_A: .long 0xFFFE0010 1177fbeb642SPhil EdworthyFRQCR_D: .word 0x1003 1187fbeb642SPhil Edworthy.align 2 1197fbeb642SPhil EdworthySTBCR3_A: .long 0xFFFE0408 1207fbeb642SPhil EdworthySTBCR3_D: .long 0x00000002 1217fbeb642SPhil EdworthySTBCR4_A: .long 0xFFFE040C 1227fbeb642SPhil EdworthySTBCR4_D: .word 0x0000 1237fbeb642SPhil Edworthy.align 2 1247fbeb642SPhil EdworthySTBCR5_A: .long 0xFFFE0410 1257fbeb642SPhil EdworthySTBCR5_D: .long 0x00000010 1267fbeb642SPhil EdworthySTBCR6_A: .long 0xFFFE0414 1277fbeb642SPhil EdworthySTBCR6_D: .long 0x00000002 1287fbeb642SPhil EdworthySTBCR7_A: .long 0xFFFE0418 1297fbeb642SPhil EdworthySTBCR7_D: .long 0x0000002A 1307fbeb642SPhil EdworthySTBCR8_A: .long 0xFFFE041C 1317fbeb642SPhil EdworthySTBCR8_D: .long 0x0000007E 1327fbeb642SPhil EdworthyPJCR1_A: .long 0xFFFE390C 1337fbeb642SPhil EdworthyPJCR1_D1: .word 0x0000 1347fbeb642SPhil EdworthyPJCR1_D2: .word 0x0022 1357fbeb642SPhil EdworthyPJCR2_A: .long 0xFFFE390A 1367fbeb642SPhil EdworthyPJCR2_D: .word 0x0000 1377fbeb642SPhil Edworthy.align 2 1387fbeb642SPhil EdworthyPJIOR0_A: .long 0xFFFE3912 1397fbeb642SPhil EdworthyPJIOR0_D1: .word 0x0FC0 1407fbeb642SPhil EdworthyPJIOR0_D2: .word 0x0FE0 1417fbeb642SPhil EdworthyPJDR0_A: .long 0xFFFE3916 1427fbeb642SPhil EdworthyPJDR0_D: .word 0x0FBF 1437fbeb642SPhil Edworthy.align 2 1447fbeb642SPhil EdworthyPJPR0_A: .long 0xFFFE391A 1457fbeb642SPhil EdworthyPJPR0_D: .long 0x00000FBF 1467fbeb642SPhil EdworthyPGCR2_A: .long 0xFFFE38CA 1477fbeb642SPhil EdworthyPGCR2_D: .word 0x0000 1487fbeb642SPhil Edworthy.align 2 1497fbeb642SPhil EdworthyPGIOR0_A: .long 0xFFFE38D2 1507fbeb642SPhil EdworthyPGIOR0_D: .word 0x03F0 1517fbeb642SPhil Edworthy.align 2 1527fbeb642SPhil EdworthyWTCSR_A: .long 0xFFFE0000 1537fbeb642SPhil EdworthyWTCSR_D0: .word 0x0000 1547fbeb642SPhil EdworthyWTCSR_D1: .word 0x0000 1557fbeb642SPhil EdworthyWTCNT_A: .long 0xFFFE0002 1567fbeb642SPhil EdworthyWTCNT_D: .word 0x0000 1577fbeb642SPhil Edworthy.align 2 1587fbeb642SPhil EdworthyPCCR0_A: .long 0xFFFE384E 1597fbeb642SPhil EdworthyPDCR0_A: .long 0xFFFE386E 1607fbeb642SPhil EdworthyPDCR1_A: .long 0xFFFE386C 1617fbeb642SPhil EdworthyPDCR2_A: .long 0xFFFE386A 1627fbeb642SPhil EdworthyPDCR3_A: .long 0xFFFE3868 1637fbeb642SPhil EdworthyPBCR0_A: .long 0xFFFE382E 1647fbeb642SPhil EdworthyPBCR1_A: .long 0xFFFE382C 1657fbeb642SPhil EdworthyPBCR2_A: .long 0xFFFE382A 1667fbeb642SPhil EdworthyPBCR3_A: .long 0xFFFE3828 1677fbeb642SPhil EdworthyPBCR4_A: .long 0xFFFE3826 1687fbeb642SPhil EdworthyPBCR5_A: .long 0xFFFE3824 1697fbeb642SPhil EdworthyPCCR0_D: .word 0x1111 1707fbeb642SPhil EdworthyPDCR0_D: .word 0x1111 1717fbeb642SPhil EdworthyPDCR1_D: .word 0x1111 1727fbeb642SPhil EdworthyPDCR2_D: .word 0x1111 1737fbeb642SPhil EdworthyPDCR3_D: .word 0x1111 1747fbeb642SPhil EdworthyPBCR0_D: .word 0x1110 1757fbeb642SPhil EdworthyPBCR1_D: .word 0x1111 1767fbeb642SPhil EdworthyPBCR2_D: .word 0x1111 1777fbeb642SPhil EdworthyPBCR3_D: .word 0x1111 1787fbeb642SPhil EdworthyPBCR4_D: .word 0x1111 1797fbeb642SPhil EdworthyPBCR5_D: .word 0x0111 1807fbeb642SPhil Edworthy.align 2 1817fbeb642SPhil EdworthyCS0WCR_A: .long 0xFFFC0028 1827fbeb642SPhil EdworthyCS0WCR_D: .long 0x00000B41 1837fbeb642SPhil EdworthyCS0BCR_A: .long 0xFFFC0004 1847fbeb642SPhil EdworthyCS0BCR_D: .long 0x10000400 1857fbeb642SPhil EdworthyPJCR0_A: .long 0xFFFE390E 186f8abfdefSPhil EdworthyPJCR0_D: .word 0x3300 1877fbeb642SPhil Edworthy.align 2 1887fbeb642SPhil EdworthyCS2WCR_A: .long 0xFFFC0030 1897fbeb642SPhil EdworthyCS2WCR_D: .long 0x00000B01 1907fbeb642SPhil EdworthyPCCR2_A: .long 0xFFFE384A 1917fbeb642SPhil EdworthyPCCR2_D: .word 0x0001 1927fbeb642SPhil Edworthy.align 2 1937fbeb642SPhil EdworthyPCCR1_A: .long 0xFFFE384C 1947fbeb642SPhil EdworthyPCCR1_D: .word 0x1111 1957fbeb642SPhil Edworthy.align 2 1967fbeb642SPhil EdworthyCS3BCR_A: .long 0xFFFC0010 1977fbeb642SPhil EdworthyCS3BCR_D: .long 0x00004400 1987fbeb642SPhil EdworthyCS3WCR_A: .long 0xFFFC0034 1997fbeb642SPhil EdworthyCS3WCR_D: .long 0x0000288A 2007fbeb642SPhil EdworthySDCR_A: .long 0xFFFC004C 2017fbeb642SPhil EdworthySDCR_D: .long 0x00000812 2027fbeb642SPhil EdworthyRTCOR_A: .long 0xFFFC0058 2037fbeb642SPhil EdworthyRTCOR_D: .long 0xA55A0046 2047fbeb642SPhil EdworthyRTCSR_A: .long 0xFFFC0050 2057fbeb642SPhil EdworthyRTCSR_D: .long 0xA55A0010 2067fbeb642SPhil EdworthyIBNR_A: .long 0xFFFE080E 2077fbeb642SPhil EdworthyIBNR_D: .word 0x0000 2087fbeb642SPhil Edworthy.align 2 2097fbeb642SPhil EdworthySDRAM_MODE: .long 0xFFFC5040 2107fbeb642SPhil EdworthyREPEAT_D: .long 0x00000085 211