1acd3e30dSNobuhiro Iwamatsu /* 2acd3e30dSNobuhiro Iwamatsu * Copyright (C) 2007 Nobuhiro Iwamatsu 3acd3e30dSNobuhiro Iwamatsu * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 4acd3e30dSNobuhiro Iwamatsu * 5acd3e30dSNobuhiro Iwamatsu * u-boot/board/r7780mp/r7780mp.h 6acd3e30dSNobuhiro Iwamatsu * 7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8acd3e30dSNobuhiro Iwamatsu */ 9acd3e30dSNobuhiro Iwamatsu 10acd3e30dSNobuhiro Iwamatsu #ifndef _BOARD_R7780MP_R7780MP_H_ 11acd3e30dSNobuhiro Iwamatsu #define _BOARD_R7780MP_R7780MP_H_ 12acd3e30dSNobuhiro Iwamatsu 13acd3e30dSNobuhiro Iwamatsu /* R7780MP's FPGA register map */ 14acd3e30dSNobuhiro Iwamatsu #define FPGA_BASE 0xa4000000 15acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLMSK (FPGA_BASE + 0x00) 16acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLMON (FPGA_BASE + 0x02) 17acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLPRI1 (FPGA_BASE + 0x04) 18acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLPRI2 (FPGA_BASE + 0x06) 19acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLPRI3 (FPGA_BASE + 0x08) 20acd3e30dSNobuhiro Iwamatsu #define FPGA_IRLPRI4 (FPGA_BASE + 0x0A) 21acd3e30dSNobuhiro Iwamatsu #define FPGA_RSTCTL (FPGA_BASE + 0x0C) 22acd3e30dSNobuhiro Iwamatsu #define FPGA_PCIBD (FPGA_BASE + 0x0E) 23acd3e30dSNobuhiro Iwamatsu #define FPGA_PCICD (FPGA_BASE + 0x10) 24acd3e30dSNobuhiro Iwamatsu #define FPGA_EXTGIO (FPGA_BASE + 0x16) 25acd3e30dSNobuhiro Iwamatsu #define FPGA_IVDRMON (FPGA_BASE + 0x18) 26acd3e30dSNobuhiro Iwamatsu #define FPGA_IVDRCR (FPGA_BASE + 0x1A) 27acd3e30dSNobuhiro Iwamatsu #define FPGA_OBLED (FPGA_BASE + 0x1C) 28acd3e30dSNobuhiro Iwamatsu #define FPGA_OBSW (FPGA_BASE + 0x1E) 29acd3e30dSNobuhiro Iwamatsu #define FPGA_TPCTL (FPGA_BASE + 0x100) 30acd3e30dSNobuhiro Iwamatsu #define FPGA_TPDCKCTL (FPGA_BASE + 0x102) 31acd3e30dSNobuhiro Iwamatsu #define FPGA_TPCLR (FPGA_BASE + 0x104) 32acd3e30dSNobuhiro Iwamatsu #define FPGA_TPXPOS (FPGA_BASE + 0x106) 33acd3e30dSNobuhiro Iwamatsu #define FPGA_TPYPOS (FPGA_BASE + 0x108) 34acd3e30dSNobuhiro Iwamatsu #define FPGA_DBSW (FPGA_BASE + 0x200) 35acd3e30dSNobuhiro Iwamatsu #define FPGA_VERSION (FPGA_BASE + 0x700) 36acd3e30dSNobuhiro Iwamatsu #define FPGA_CFCTL (FPGA_BASE + 0x300) 37acd3e30dSNobuhiro Iwamatsu #define FPGA_CFPOW (FPGA_BASE + 0x302) 38acd3e30dSNobuhiro Iwamatsu #define FPGA_CFCDINTCLR (FPGA_BASE + 0x304) 39acd3e30dSNobuhiro Iwamatsu #define FPGA_PMR (FPGA_BASE + 0x900) 40acd3e30dSNobuhiro Iwamatsu 41acd3e30dSNobuhiro Iwamatsu #endif /* _BOARD_R7780RP_R7780RP_H_ */ 42