1127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
2127f9ae5SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2008
3127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Grazvydas Ignotas <notasas@gmail.com>
4127f9ae5SJean-Christophe PLAGNIOL-VILLARD *
5127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
6127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Richard Woodruff <r-woodruff2@ti.com>
7127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Syed Mohammed Khasim <khasim@ti.com>
8127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Sunil Kumar <sunilsaini05@gmail.com>
9127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Shashi Ranjan <shashiranjanmca05@gmail.com>
10127f9ae5SJean-Christophe PLAGNIOL-VILLARD *
11127f9ae5SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2004-2008
12127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Texas Instruments, <www.ti.com>
13127f9ae5SJean-Christophe PLAGNIOL-VILLARD *
141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
15127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
16127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <common.h>
17127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <twl4030.h>
18127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
197cad446bSGrazvydas Ignotas #include <asm/gpio.h>
2086c5c544STom Rini #include <asm/arch/mmc_host_def.h>
21127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/mux.h>
22080a46eaSAneesh V #include <asm/arch/gpio.h>
23127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/sys_proto.h>
24127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/mach-types.h>
25127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include "pandora.h"
26127f9ae5SJean-Christophe PLAGNIOL-VILLARD
2729565326SJohn Rigby DECLARE_GLOBAL_DATA_PTR;
2829565326SJohn Rigby
295246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBCHEN (1 << 4)
305246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
315246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBISEL_500UA 2
325246d01eSGrazvydas Ignotas
337cad446bSGrazvydas Ignotas #define CONTROL_WKUP_CTRL 0x48002a5c
347cad446bSGrazvydas Ignotas #define GPIO_IO_PWRDNZ (1 << 6)
357cad446bSGrazvydas Ignotas #define PBIASLITEVMODE1 (1 << 8)
367cad446bSGrazvydas Ignotas
37127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
38127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: board_init
39127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Early hardware init.
40127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
board_init(void)41127f9ae5SJean-Christophe PLAGNIOL-VILLARD int board_init(void)
42127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
43127f9ae5SJean-Christophe PLAGNIOL-VILLARD gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
44127f9ae5SJean-Christophe PLAGNIOL-VILLARD /* board id for Linux */
45127f9ae5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
46127f9ae5SJean-Christophe PLAGNIOL-VILLARD /* boot param addr */
47127f9ae5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
48127f9ae5SJean-Christophe PLAGNIOL-VILLARD
49127f9ae5SJean-Christophe PLAGNIOL-VILLARD return 0;
50127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
51127f9ae5SJean-Christophe PLAGNIOL-VILLARD
set_output_gpio(unsigned int gpio,int value)527cad446bSGrazvydas Ignotas static void set_output_gpio(unsigned int gpio, int value)
537cad446bSGrazvydas Ignotas {
547cad446bSGrazvydas Ignotas int ret;
557cad446bSGrazvydas Ignotas
567cad446bSGrazvydas Ignotas ret = gpio_request(gpio, "");
577cad446bSGrazvydas Ignotas if (ret != 0) {
587cad446bSGrazvydas Ignotas printf("could not request GPIO %u\n", gpio);
597cad446bSGrazvydas Ignotas return;
607cad446bSGrazvydas Ignotas }
617cad446bSGrazvydas Ignotas ret = gpio_direction_output(gpio, value);
627cad446bSGrazvydas Ignotas if (ret != 0)
637cad446bSGrazvydas Ignotas printf("could not set GPIO %u to %d\n", gpio, value);
647cad446bSGrazvydas Ignotas }
657cad446bSGrazvydas Ignotas
66127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
67127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: misc_init_r
68127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Configure board specific parts
69127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
misc_init_r(void)70127f9ae5SJean-Christophe PLAGNIOL-VILLARD int misc_init_r(void)
71127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
727cad446bSGrazvydas Ignotas t2_t *t2_base = (t2_t *)T2_BASE;
737cad446bSGrazvydas Ignotas u32 pbias_lite;
74127f9ae5SJean-Christophe PLAGNIOL-VILLARD
75ead39d7aSGrazvydas Ignotas twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
76127f9ae5SJean-Christophe PLAGNIOL-VILLARD
777cad446bSGrazvydas Ignotas /* set up dual-voltage GPIOs to 1.8V */
787cad446bSGrazvydas Ignotas pbias_lite = readl(&t2_base->pbias_lite);
797cad446bSGrazvydas Ignotas pbias_lite &= ~PBIASLITEVMODE1;
807cad446bSGrazvydas Ignotas pbias_lite |= PBIASLITEPWRDNZ1;
817cad446bSGrazvydas Ignotas writel(pbias_lite, &t2_base->pbias_lite);
827cad446bSGrazvydas Ignotas if (get_cpu_family() == CPU_OMAP36XX)
837cad446bSGrazvydas Ignotas writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
847cad446bSGrazvydas Ignotas CONTROL_WKUP_CTRL);
85127f9ae5SJean-Christophe PLAGNIOL-VILLARD
867cad446bSGrazvydas Ignotas /* make sure audio and BT chips are in powerdown state */
877cad446bSGrazvydas Ignotas set_output_gpio(14, 0);
887cad446bSGrazvydas Ignotas set_output_gpio(15, 0);
897cad446bSGrazvydas Ignotas set_output_gpio(118, 0);
907cad446bSGrazvydas Ignotas
917cad446bSGrazvydas Ignotas /* enable USB supply */
927cad446bSGrazvydas Ignotas set_output_gpio(164, 1);
937cad446bSGrazvydas Ignotas
947cad446bSGrazvydas Ignotas /* wifi needs a short pulse to enter powersave state */
957cad446bSGrazvydas Ignotas set_output_gpio(23, 1);
967cad446bSGrazvydas Ignotas udelay(5000);
977cad446bSGrazvydas Ignotas gpio_direction_output(23, 0);
98127f9ae5SJean-Christophe PLAGNIOL-VILLARD
995246d01eSGrazvydas Ignotas /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
1005246d01eSGrazvydas Ignotas twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
1010208aaf6SNishanth Menon TWL4030_PM_RECEIVER_BB_CFG,
1025246d01eSGrazvydas Ignotas TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
1030208aaf6SNishanth Menon TWL4030_BB_CFG_BBISEL_500UA);
1045246d01eSGrazvydas Ignotas
105679f82c3SPaul Kocialkowski omap_die_id_display();
106127f9ae5SJean-Christophe PLAGNIOL-VILLARD
107127f9ae5SJean-Christophe PLAGNIOL-VILLARD return 0;
108127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
109127f9ae5SJean-Christophe PLAGNIOL-VILLARD
110127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
111127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: set_muxconf_regs
112127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Setting up the configuration Mux registers specific to the
113127f9ae5SJean-Christophe PLAGNIOL-VILLARD * hardware. Many pins need to be moved from protect to primary
114127f9ae5SJean-Christophe PLAGNIOL-VILLARD * mode.
115127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
set_muxconf_regs(void)116127f9ae5SJean-Christophe PLAGNIOL-VILLARD void set_muxconf_regs(void)
117127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
118127f9ae5SJean-Christophe PLAGNIOL-VILLARD MUX_PANDORA();
11910cd73bfSGrazvydas Ignotas if (get_cpu_family() == CPU_OMAP36XX) {
12010cd73bfSGrazvydas Ignotas MUX_PANDORA_3730();
12110cd73bfSGrazvydas Ignotas }
122127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
12386c5c544STom Rini
124*4aa2ba3aSMasahiro Yamada #ifdef CONFIG_MMC
board_mmc_init(bd_t * bis)12586c5c544STom Rini int board_mmc_init(bd_t *bis)
12686c5c544STom Rini {
127e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1);
12886c5c544STom Rini }
129aac5450eSPaul Kocialkowski
board_mmc_power_init(void)130aac5450eSPaul Kocialkowski void board_mmc_power_init(void)
131aac5450eSPaul Kocialkowski {
132aac5450eSPaul Kocialkowski twl4030_power_mmc_init(0);
133aac5450eSPaul Kocialkowski }
13486c5c544STom Rini #endif
135