1 /* 2 * Maintainer : Steve Sakoman <steve@sakoman.com> 3 * 4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Syed Mohammed Khasim <khasim@ti.com> 7 * Sunil Kumar <sunilsaini05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 9 * 10 * (C) Copyright 2004-2008 11 * Texas Instruments, <www.ti.com> 12 * 13 * See file CREDITS for list of people who contributed to this 14 * project. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 #include <common.h> 32 #include <netdev.h> 33 #include <twl4030.h> 34 #include <asm/io.h> 35 #include <asm/arch/mux.h> 36 #include <asm/arch/mem.h> 37 #include <asm/arch/sys_proto.h> 38 #include <asm/arch/gpio.h> 39 #include <asm/mach-types.h> 40 #include "overo.h" 41 42 #if defined(CONFIG_CMD_NET) 43 static void setup_net_chip(void); 44 #endif 45 46 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */ 47 static const u32 gpmc_lan_config[] = { 48 NET_LAN9221_GPMC_CONFIG1, 49 NET_LAN9221_GPMC_CONFIG2, 50 NET_LAN9221_GPMC_CONFIG3, 51 NET_LAN9221_GPMC_CONFIG4, 52 NET_LAN9221_GPMC_CONFIG5, 53 NET_LAN9221_GPMC_CONFIG6, 54 /*CONFIG7- computed as params */ 55 }; 56 57 /* 58 * Routine: board_init 59 * Description: Early hardware init. 60 */ 61 int board_init(void) 62 { 63 DECLARE_GLOBAL_DATA_PTR; 64 65 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 66 /* board id for Linux */ 67 gd->bd->bi_arch_number = MACH_TYPE_OVERO; 68 /* boot param addr */ 69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 70 71 return 0; 72 } 73 74 /* 75 * Routine: get_board_revision 76 * Description: Returns the board revision 77 */ 78 int get_board_revision(void) 79 { 80 int revision; 81 82 if (!omap_request_gpio(112) && 83 !omap_request_gpio(113) && 84 !omap_request_gpio(115)) { 85 86 omap_set_gpio_direction(112, 1); 87 omap_set_gpio_direction(113, 1); 88 omap_set_gpio_direction(115, 1); 89 90 revision = omap_get_gpio_datain(115) << 2 | 91 omap_get_gpio_datain(113) << 1 | 92 omap_get_gpio_datain(112); 93 94 omap_free_gpio(112); 95 omap_free_gpio(113); 96 omap_free_gpio(115); 97 } else { 98 printf("Error: unable to acquire board revision GPIOs\n"); 99 revision = -1; 100 } 101 102 return revision; 103 } 104 105 /* 106 * Routine: misc_init_r 107 * Description: Configure board specific parts 108 */ 109 int misc_init_r(void) 110 { 111 twl4030_power_init(); 112 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 113 114 #if defined(CONFIG_CMD_NET) 115 setup_net_chip(); 116 #endif 117 118 printf("Board revision: %d\n", get_board_revision()); 119 dieid_num_r(); 120 121 return 0; 122 } 123 124 /* 125 * Routine: set_muxconf_regs 126 * Description: Setting up the configuration Mux registers specific to the 127 * hardware. Many pins need to be moved from protect to primary 128 * mode. 129 */ 130 void set_muxconf_regs(void) 131 { 132 MUX_OVERO(); 133 } 134 135 #if defined(CONFIG_CMD_NET) 136 /* 137 * Routine: setup_net_chip 138 * Description: Setting up the configuration GPMC registers specific to the 139 * Ethernet hardware. 140 */ 141 static void setup_net_chip(void) 142 { 143 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; 144 145 /* first lan chip */ 146 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, 147 GPMC_SIZE_16M); 148 149 /* second lan chip */ 150 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000, 151 GPMC_SIZE_16M); 152 153 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ 154 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); 155 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */ 156 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); 157 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */ 158 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, 159 &ctrl_base->gpmc_nadv_ale); 160 161 /* Make GPIO 64 as output pin and send a magic pulse through it */ 162 if (!omap_request_gpio(64)) { 163 omap_set_gpio_direction(64, 0); 164 omap_set_gpio_dataout(64, 1); 165 udelay(1); 166 omap_set_gpio_dataout(64, 0); 167 udelay(1); 168 omap_set_gpio_dataout(64, 1); 169 } 170 } 171 #endif 172 173 int board_eth_init(bd_t *bis) 174 { 175 int rc = 0; 176 #ifdef CONFIG_SMC911X 177 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); 178 #endif 179 return rc; 180 } 181