1*f7dc4ac3STom Warren /* 2*f7dc4ac3STom Warren * (C) Copyright 2013-2014 3*f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 4*f7dc4ac3STom Warren * 5*f7dc4ac3STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*f7dc4ac3STom Warren */ 7*f7dc4ac3STom Warren 8*f7dc4ac3STom Warren #include <common.h> 9*f7dc4ac3STom Warren #include <asm-generic/gpio.h> 10*f7dc4ac3STom Warren #include <asm/arch/gpio.h> 11*f7dc4ac3STom Warren #include <asm/arch/gp_padctrl.h> 12*f7dc4ac3STom Warren #include <asm/arch/pinmux.h> 13*f7dc4ac3STom Warren #include "pinmux-config-venice2.h" 14*f7dc4ac3STom Warren #include <i2c.h> 15*f7dc4ac3STom Warren 16*f7dc4ac3STom Warren /* 17*f7dc4ac3STom Warren * Routine: pinmux_init 18*f7dc4ac3STom Warren * Description: Do individual peripheral pinmux configs 19*f7dc4ac3STom Warren */ 20*f7dc4ac3STom Warren void pinmux_init(void) 21*f7dc4ac3STom Warren { 22*f7dc4ac3STom Warren pinmux_config_table(tegra124_pinmux_set_nontristate, 23*f7dc4ac3STom Warren ARRAY_SIZE(tegra124_pinmux_set_nontristate)); 24*f7dc4ac3STom Warren 25*f7dc4ac3STom Warren pinmux_config_table(tegra124_pinmux_common, 26*f7dc4ac3STom Warren ARRAY_SIZE(tegra124_pinmux_common)); 27*f7dc4ac3STom Warren 28*f7dc4ac3STom Warren pinmux_config_table(unused_pins_lowpower, 29*f7dc4ac3STom Warren ARRAY_SIZE(unused_pins_lowpower)); 30*f7dc4ac3STom Warren 31*f7dc4ac3STom Warren /* Initialize any non-default pad configs (APB_MISC_GP regs) */ 32*f7dc4ac3STom Warren padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl)); 33*f7dc4ac3STom Warren } 34