xref: /rk3399_rockchip-uboot/board/nvidia/seaboard/seaboard.c (revision a04eba99f5a00aff54bef32cafa986830b094532)
1f4ef6668STom Warren /*
2f4ef6668STom Warren  *  (C) Copyright 2010,2011
3f4ef6668STom Warren  *  NVIDIA Corporation <www.nvidia.com>
4f4ef6668STom Warren  *
5f4ef6668STom Warren  * See file CREDITS for list of people who contributed to this
6f4ef6668STom Warren  * project.
7f4ef6668STom Warren  *
8f4ef6668STom Warren  * This program is free software; you can redistribute it and/or
9f4ef6668STom Warren  * modify it under the terms of the GNU General Public License as
10f4ef6668STom Warren  * published by the Free Software Foundation; either version 2 of
11f4ef6668STom Warren  * the License, or (at your option) any later version.
12f4ef6668STom Warren  *
13f4ef6668STom Warren  * This program is distributed in the hope that it will be useful,
14f4ef6668STom Warren  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15f4ef6668STom Warren  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16f4ef6668STom Warren  * GNU General Public License for more details.
17f4ef6668STom Warren  *
18f4ef6668STom Warren  * You should have received a copy of the GNU General Public License
19f4ef6668STom Warren  * along with this program; if not, write to the Free Software
20f4ef6668STom Warren  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21f4ef6668STom Warren  * MA 02111-1307 USA
22f4ef6668STom Warren  */
23f4ef6668STom Warren 
24f4ef6668STom Warren #include <common.h>
25f4ef6668STom Warren #include <asm/io.h>
26f4ef6668STom Warren #include <asm/arch/tegra2.h>
27ae03661fSStephen Warren #include <asm/arch/pinmux.h>
28ccf7988bSTom Warren #include <asm/gpio.h>
29ccf7988bSTom Warren #ifdef CONFIG_TEGRA2_MMC
30ccf7988bSTom Warren #include <mmc.h>
31ccf7988bSTom Warren #endif
32ae03661fSStephen Warren #include "../common/board.h"
33f4ef6668STom Warren 
34*a04eba99SSimon Glass /* TODO: Remove this code when the SPI switch is working */
35*a04eba99SSimon Glass #ifndef CONFIG_SPI_UART_SWITCH
36f4ef6668STom Warren /*
37d5ef19b9SStephen Warren  * Routine: gpio_config_uart_seaboard
38f4ef6668STom Warren  * Description: Force GPIO_PI3 low on Seaboard so UART4 works.
39f4ef6668STom Warren  */
40d5ef19b9SStephen Warren static void gpio_config_uart_seaboard(void)
41f4ef6668STom Warren {
42f4ef6668STom Warren 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
435fac236aSStephen Warren 	gpio_request(GPIO_PI3, NULL);
445fac236aSStephen Warren 	gpio_direction_output(GPIO_PI3, 0);
45f4ef6668STom Warren }
46ccf7988bSTom Warren 
47d5ef19b9SStephen Warren void gpio_config_uart(void)
48d5ef19b9SStephen Warren {
49d5ef19b9SStephen Warren 	if (machine_is_ventana())
50d5ef19b9SStephen Warren 		return;
51d5ef19b9SStephen Warren 	gpio_config_uart_seaboard();
52d5ef19b9SStephen Warren }
53*a04eba99SSimon Glass #endif
54d5ef19b9SStephen Warren 
55ccf7988bSTom Warren #ifdef CONFIG_TEGRA2_MMC
56ccf7988bSTom Warren /*
57ae03661fSStephen Warren  * Routine: pin_mux_mmc
58ae03661fSStephen Warren  * Description: setup the pin muxes/tristate values for the SDMMC(s)
59ae03661fSStephen Warren  */
60ae03661fSStephen Warren static void pin_mux_mmc(void)
61ae03661fSStephen Warren {
62ae03661fSStephen Warren 	/* SDMMC4: config 3, x8 on 2nd set of pins */
63ae03661fSStephen Warren 	pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
64ae03661fSStephen Warren 	pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
65ae03661fSStephen Warren 	pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
66ae03661fSStephen Warren 
67ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_ATB);
68ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_GMA);
69ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_GME);
70ae03661fSStephen Warren 
71ae03661fSStephen Warren 	/* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
72ae03661fSStephen Warren 	pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
73ae03661fSStephen Warren 	pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
74ae03661fSStephen Warren 	pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
75ae03661fSStephen Warren 
76ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_SDC);
77ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_SDD);
78ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_SDB);
79ae03661fSStephen Warren 
80ae03661fSStephen Warren 	/* For power GPIO PI6 */
81ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_ATA);
82ae03661fSStephen Warren 	/* For CD GPIO PI5 */
83ae03661fSStephen Warren 	pinmux_tristate_disable(PINGRP_ATC);
84ae03661fSStephen Warren }
85ae03661fSStephen Warren 
86ccf7988bSTom Warren /* this is a weak define that we are overriding */
87ae03661fSStephen Warren int board_mmc_init(bd_t *bd)
88ae03661fSStephen Warren {
89ae03661fSStephen Warren 	debug("board_mmc_init called\n");
90ae03661fSStephen Warren 
91ae03661fSStephen Warren 	/* Enable muxes, etc. for SDMMC controllers */
92ae03661fSStephen Warren 	pin_mux_mmc();
93ae03661fSStephen Warren 
94ae03661fSStephen Warren 	debug("board_mmc_init: init eMMC\n");
95ae03661fSStephen Warren 	/* init dev 0, eMMC chip, with 4-bit bus */
96ae03661fSStephen Warren 	/* The board has an 8-bit bus, but 8-bit doesn't work yet */
979877841fSStephen Warren 	tegra2_mmc_init(0, 4, -1, -1);
98ae03661fSStephen Warren 
99ae03661fSStephen Warren 	debug("board_mmc_init: init SD slot\n");
100ae03661fSStephen Warren 	/* init dev 1, SD slot, with 4-bit bus */
1019877841fSStephen Warren 	tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
102ccf7988bSTom Warren 
103ccf7988bSTom Warren 	return 0;
104ccf7988bSTom Warren }
105ccf7988bSTom Warren #endif
106