xref: /rk3399_rockchip-uboot/board/nvidia/seaboard/seaboard.c (revision 19d7bf3d868383bf504c1dd2b4618fbf2b3dc20e)
1f4ef6668STom Warren /*
2f4ef6668STom Warren  *  (C) Copyright 2010,2011
3f4ef6668STom Warren  *  NVIDIA Corporation <www.nvidia.com>
4f4ef6668STom Warren  *
51a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
6f4ef6668STom Warren  */
7f4ef6668STom Warren 
8f4ef6668STom Warren #include <common.h>
9f4ef6668STom Warren #include <asm/io.h>
10150c2493STom Warren #include <asm/arch/tegra.h>
11*19d7bf3dSJeroen Hofstee #include <asm/arch-tegra/board.h>
12ca28090dSSimon Glass #include <asm/arch/clock.h>
13ca28090dSSimon Glass #include <asm/arch/funcmux.h>
14a2ab6b7dSStephen Warren #include <asm/arch/gpio.h>
15ae03661fSStephen Warren #include <asm/arch/pinmux.h>
16ccf7988bSTom Warren #include <asm/gpio.h>
17f4ef6668STom Warren 
18a04eba99SSimon Glass /* TODO: Remove this code when the SPI switch is working */
199000652dSAllen Martin #if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA)
200cd10c7aSLucas Stach void gpio_early_init_uart(void)
21d5ef19b9SStephen Warren {
22a2ab6b7dSStephen Warren 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
23a2ab6b7dSStephen Warren #ifndef CONFIG_SPL_BUILD
24a2ab6b7dSStephen Warren 	gpio_request(GPIO_PI3, NULL);
25a2ab6b7dSStephen Warren #endif
262fccd2d9SSimon Glass 	tegra_spl_gpio_direction_output(GPIO_PI3, 0);
27d5ef19b9SStephen Warren }
28a04eba99SSimon Glass #endif
29d5ef19b9SStephen Warren 
303f82d89dSTom Warren #ifdef CONFIG_TEGRA_MMC
31ccf7988bSTom Warren /*
32ae03661fSStephen Warren  * Routine: pin_mux_mmc
33ae03661fSStephen Warren  * Description: setup the pin muxes/tristate values for the SDMMC(s)
34ae03661fSStephen Warren  */
35c9aa831eSTom Warren void pin_mux_mmc(void)
36ae03661fSStephen Warren {
37ca28090dSSimon Glass 	funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
38ca28090dSSimon Glass 	funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
39ae03661fSStephen Warren 
40ae03661fSStephen Warren 	/* For power GPIO PI6 */
4170ad375eSStephen Warren 	pinmux_tristate_disable(PMUX_PINGRP_ATA);
42ae03661fSStephen Warren 	/* For CD GPIO PI5 */
4370ad375eSStephen Warren 	pinmux_tristate_disable(PMUX_PINGRP_ATC);
44ae03661fSStephen Warren }
45ccf7988bSTom Warren #endif
46f10393e5SSimon Glass 
47f10393e5SSimon Glass void pin_mux_usb(void)
48f10393e5SSimon Glass {
49f10393e5SSimon Glass 	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
5070ad375eSStephen Warren 	pinmux_tristate_disable(PMUX_PINGRP_SLXK);
51f10393e5SSimon Glass }
52