1f01b631fSTom Warren /*
28ca79b2fSTom Warren * (C) Copyright 2010-2013
3f01b631fSTom Warren * NVIDIA Corporation <www.nvidia.com>
4f01b631fSTom Warren *
51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
6f01b631fSTom Warren */
7f01b631fSTom Warren
8f01b631fSTom Warren #include <common.h>
9b0e6ef46SSimon Glass #include <dm.h>
10f01b631fSTom Warren #include <asm/arch/pinmux.h>
118ca79b2fSTom Warren #include <asm/arch/gp_padctrl.h>
125a2c96a0SThierry Reding #include <asm/arch/gpio.h>
135a2c96a0SThierry Reding #include <asm/gpio.h>
14f01b631fSTom Warren #include "pinmux-config-cardhu.h"
15190be1f9STom Warren #include <i2c.h>
16190be1f9STom Warren
17190be1f9STom Warren #define PMU_I2C_ADDRESS 0x2D
18190be1f9STom Warren #define MAX_I2C_RETRY 3
19f01b631fSTom Warren
20f01b631fSTom Warren /*
21f01b631fSTom Warren * Routine: pinmux_init
22f01b631fSTom Warren * Description: Do individual peripheral pinmux configs
23f01b631fSTom Warren */
pinmux_init(void)24f01b631fSTom Warren void pinmux_init(void)
25f01b631fSTom Warren {
26dfb42fc9SStephen Warren pinmux_config_pingrp_table(tegra3_pinmux_common,
27f01b631fSTom Warren ARRAY_SIZE(tegra3_pinmux_common));
28f01b631fSTom Warren
29dfb42fc9SStephen Warren pinmux_config_pingrp_table(unused_pins_lowpower,
30f01b631fSTom Warren ARRAY_SIZE(unused_pins_lowpower));
318ca79b2fSTom Warren
328ca79b2fSTom Warren /* Initialize any non-default pad configs (APB_MISC_GP regs) */
33dfb42fc9SStephen Warren pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
34f01b631fSTom Warren }
35190be1f9STom Warren
36*1d2c0506SMasahiro Yamada #if defined(CONFIG_MMC_SDHCI_TEGRA)
37190be1f9STom Warren /*
38190be1f9STom Warren * Do I2C/PMU writes to bring up SD card bus power
39190be1f9STom Warren *
40190be1f9STom Warren */
board_sdmmc_voltage_init(void)41190be1f9STom Warren void board_sdmmc_voltage_init(void)
42190be1f9STom Warren {
43b0e6ef46SSimon Glass struct udevice *dev;
44190be1f9STom Warren uchar reg, data_buffer[1];
45b0e6ef46SSimon Glass int ret;
46190be1f9STom Warren int i;
47190be1f9STom Warren
4825ab4b03SSimon Glass ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
49b0e6ef46SSimon Glass if (ret) {
50b0e6ef46SSimon Glass debug("%s: Cannot find PMIC I2C chip\n", __func__);
51b0e6ef46SSimon Glass return;
52b0e6ef46SSimon Glass }
53190be1f9STom Warren
54190be1f9STom Warren /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
55190be1f9STom Warren data_buffer[0] = 0x65;
56190be1f9STom Warren reg = 0x32;
57190be1f9STom Warren
58190be1f9STom Warren for (i = 0; i < MAX_I2C_RETRY; ++i) {
59f9a4c2daSSimon Glass if (dm_i2c_write(dev, reg, data_buffer, 1))
60190be1f9STom Warren udelay(100);
61190be1f9STom Warren }
62190be1f9STom Warren
63190be1f9STom Warren /* TPS659110: GPIO7_REG = PDEN, output a 1 to EN_3V3_SYS */
64190be1f9STom Warren data_buffer[0] = 0x09;
65190be1f9STom Warren reg = 0x67;
66190be1f9STom Warren
67190be1f9STom Warren for (i = 0; i < MAX_I2C_RETRY; ++i) {
68f9a4c2daSSimon Glass if (dm_i2c_write(dev, reg, data_buffer, 1))
69190be1f9STom Warren udelay(100);
70190be1f9STom Warren }
71190be1f9STom Warren }
72190be1f9STom Warren
73190be1f9STom Warren /*
74190be1f9STom Warren * Routine: pin_mux_mmc
75190be1f9STom Warren * Description: setup the MMC muxes, power rails, etc.
76190be1f9STom Warren */
pin_mux_mmc(void)77190be1f9STom Warren void pin_mux_mmc(void)
78190be1f9STom Warren {
79190be1f9STom Warren /*
80190be1f9STom Warren * NOTE: We don't do mmc-specific pin muxes here.
81190be1f9STom Warren * They were done globally in pinmux_init().
82190be1f9STom Warren */
83190be1f9STom Warren
84190be1f9STom Warren /* Bring up the SDIO1 power rail */
85190be1f9STom Warren board_sdmmc_voltage_init();
86190be1f9STom Warren }
87190be1f9STom Warren #endif /* MMC */
885a2c96a0SThierry Reding
895a2c96a0SThierry Reding #ifdef CONFIG_PCI_TEGRA
tegra_pcie_board_init(void)905a2c96a0SThierry Reding int tegra_pcie_board_init(void)
915a2c96a0SThierry Reding {
925a2c96a0SThierry Reding struct udevice *dev;
935a2c96a0SThierry Reding u8 addr, data[1];
945a2c96a0SThierry Reding int err;
955a2c96a0SThierry Reding
9625ab4b03SSimon Glass err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
975a2c96a0SThierry Reding if (err) {
985a2c96a0SThierry Reding debug("failed to find PMU bus\n");
995a2c96a0SThierry Reding return err;
1005a2c96a0SThierry Reding }
1015a2c96a0SThierry Reding
1025a2c96a0SThierry Reding /* TPS659110: LDO1_REG = 1.05V, ACTIVE */
1035a2c96a0SThierry Reding data[0] = 0x15;
1045a2c96a0SThierry Reding addr = 0x30;
1055a2c96a0SThierry Reding
106f9a4c2daSSimon Glass err = dm_i2c_write(dev, addr, data, 1);
1075a2c96a0SThierry Reding if (err) {
1085a2c96a0SThierry Reding debug("failed to set VDD supply\n");
1095a2c96a0SThierry Reding return err;
1105a2c96a0SThierry Reding }
1115a2c96a0SThierry Reding
1125a2c96a0SThierry Reding /* GPIO: PEX = 3.3V */
11301a97a11SStephen Warren err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
1145a2c96a0SThierry Reding if (err < 0)
1155a2c96a0SThierry Reding return err;
1165a2c96a0SThierry Reding
11701a97a11SStephen Warren gpio_direction_output(TEGRA_GPIO(L, 7), 1);
1185a2c96a0SThierry Reding
1195a2c96a0SThierry Reding /* TPS659110: LDO2_REG = 1.05V, ACTIVE */
1205a2c96a0SThierry Reding data[0] = 0x15;
1215a2c96a0SThierry Reding addr = 0x31;
1225a2c96a0SThierry Reding
123f9a4c2daSSimon Glass err = dm_i2c_write(dev, addr, data, 1);
1245a2c96a0SThierry Reding if (err) {
1255a2c96a0SThierry Reding debug("failed to set AVDD supply\n");
1265a2c96a0SThierry Reding return err;
1275a2c96a0SThierry Reding }
1285a2c96a0SThierry Reding
1295a2c96a0SThierry Reding return 0;
1305a2c96a0SThierry Reding }
1315a2c96a0SThierry Reding #endif /* PCI */
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